| 1. | EXECUTIVE SUMMARY |
| 1.1. | SoC, SiP vs chiplet |
| 1.2. | Current status of chiplet technology |
| 1.3. | Future trends in chiplet technology (1/2) |
| 1.4. | Future trends in chiplet technology (2/2) |
| 1.5. | Possible chiplet supply chain |
| 1.6. | Chiplet ecosystem across different periods |
| 1.7. | Analysis of possible chiplet supply chain (1/2) |
| 1.8. | Analysis of possible chiplet supply chain (2/2) |
| 1.9. | Opportunities unlocked by the chiplet platform |
| 1.10. | Chiplet impact |
| 1.11. | Convergence to chiplet |
| 1.12. | Chiplet adoption evolution |
| 1.13. | Market forecast coverage and methodologies |
| 1.14. | Forecast assumptions |
| 1.15. | Chiplet shipment unit forecast 2024-2035 |
| 1.16. | Chiplet market forecast 2024-2035 |
| 1.17. | Market share comparison 2024 vs 2030 |
| 1.18. | Chiplet classifications |
| 1.19. | Application markets |
| 1.20. | Potential applications of chiplet technology (1/4) |
| 1.21. | Potential applications of chiplet technology (2/4) |
| 1.22. | Potential applications of chiplet technology (3/4) |
| 1.23. | Potential applications of chiplet technology (4/4) |
| 2. | INTRODUCTION TO CHIPLETS |
| 2.1. | Why now |
| 2.2. | From monolithic chips to chiplets |
| 2.3. | What is chiplet technology |
| 2.4. | Definition of chiplet |
| 2.5. | SoC vs Chiplet |
| 2.6. | Generic chiplet integration |
| 2.7. | SiP vs Chiplet |
| 2.8. | Heterogenous integration |
| 2.9. | Technology building blocks for heterogeneous integration |
| 2.10. | Types of heterogenous integration |
| 2.11. | Different types of chiplets for computation |
| 3. | DRIVERS AND BENEFITS OF CHIPLET DESIGN |
| 3.1. | Limitations of large dies |
| 3.2. | Benefits of small chips 1 |
| 3.3. | Benefits of small chips 2 |
| 3.4. | Monolithic dies may not provide enough memory |
| 3.5. | Increasing cost with advanced processing nodes |
| 3.6. | Costs trend with processing nodes |
| 3.7. | Costs reduction with processing nodes via Chiplet design |
| 3.8. | Improved supply chain security |
| 3.9. | IP Chipletization |
| 3.10. | Chiplet as a platform |
| 3.11. | 3D IC design |
| 3.12. | Chiplet design for cost consideration |
| 3.13. | Other benefits of chiplet design |
| 3.14. | The rise of chiplets in semiconductor technology |
| 4. | CHALLENGES OF CHIPLET |
| 4.1. | Challenges with chiplets |
| 4.2. | Challenges from demand and supply angles |
| 5. | CHIPLET TECHNOLOGY AND MANUFACTURING |
| 5.1.1. | Technical structure of chiplets |
| 5.2. | Design |
| 5.2.1. | Co-design of high-performance chip-package-system |
| 5.2.2. | Chiplet design and integration |
| 5.2.3. | Challenges and solutions in EDA for chiplets (1/2) |
| 5.2.4. | Challenges and solutions in EDA for chiplets (2/2) |
| 5.2.5. | The three giants of EDA are shifting to a new battlefield |
| 5.2.6. | AI in EDA |
| 5.3. | Packaging and Assembly Technologies |
| 5.3.1. | Levels of integration |
| 5.3.2. | Traditional packaging |
| 5.3.3. | TSV enables integration beyond 2D dimension |
| 5.3.4. | From chip, package to system |
| 5.3.5. | Dimensionality of advanced packaging |
| 5.3.6. | From 1D semiconductor packaging |
| 5.3.7. | Advanced packaging 2D & 2D+ |
| 5.3.8. | Advanced packaging 2.5D & 3D |
| 5.3.9. | Advanced packaging 3.5D & 4D |
| 5.3.10. | Advanced packaging trend |
| 5.3.11. | Key elements of advanced packaging |
| 5.3.12. | Silicon stacking: A key enabler of advanced packaging |
| 5.3.13. | Trends of advanced packaging |
| 5.3.14. | Representative Examples of Advanced Packaging |
| 5.3.15. | TSMC's advanced semiconductor packaging technology portfolio |
| 5.3.16. | TSMC 2.5D packaging technology - CoWoS |
| 5.3.17. | 3D chiplet |
| 5.3.18. | Combine 3D SoIC and 2.5D backend packaging technologies |
| 5.3.19. | Intel's advanced semiconductor packaging technology portfolio |
| 5.3.20. | Intel's EMIB |
| 5.3.21. | Intel's Co-EMIB (EMIB + Foveros) |
| 5.3.22. | Samsung's advanced semiconductor packaging technology portfolio |
| 5.3.23. | Samsung's advanced packaging technologies |
| 5.3.24. | Amkor advanced semiconductor packaging solutions |
| 5.3.25. | Amkor's S-Connect |
| 5.4. | Inter-Chiplet Communication and Interconnects |
| 5.4.1. | Electrical interconnects |
| 5.4.2. | From aluminum to copper |
| 5.4.3. | Material considerations |
| 5.4.4. | Interconnect technologies for semiconductor packaging |
| 5.4.5. | Interface stack for chiplets |
| 5.4.6. | Interface for chiplet |
| 5.4.7. | D2D interface types |
| 5.4.8. | Serial vs parallel interface |
| 5.4.9. | 112G USR/XSR vs HBI |
| 5.4.10. | Proprietary D2D interface standards |
| 5.4.11. | Proprietary D2D interface standard comparison |
| 5.4.12. | Open D2D interface standards |
| 5.4.13. | Open D2D interface standards comparison |
| 5.4.14. | Universal Chiplet Interconnect Express (UCIe) |
| 5.4.15. | NVIDIA NVLink-C2C |
| 5.4.16. | Standard protocols of heterogeneous computing |
| 5.4.17. | Relationship of chiplet interfaces, bandwidth and typical packages |
| 5.4.18. | Chiplet D2D I/O matrix |
| 5.4.19. | Recommended interconnect for applications |
| 5.4.20. | Interconnect classification |
| 5.4.21. | Interconnection technology I/O pitch & density |
| 5.4.22. | Bump technologies |
| 5.4.23. | Typical bump sizes and pitches |
| 5.4.24. | Hybrid bonding |
| 5.4.25. | SoIC compared to 2.5D and 3D IC |
| 5.4.26. | Alternative technologies to electric SerDes |
| 5.4.27. | Photonics technology for chiplet |
| 5.4.28. | Limitation of electrical copper I/O |
| 5.4.29. | From discrete III-V to CPO |
| 5.4.30. | Optical integration development trends |
| 5.5. | Power Delivery and Thermal Management |
| 5.5.1. | Power delivery |
| 5.5.2. | Power delivery attributes for chiplets |
| 5.5.3. | Heat dissipation of a chip |
| 5.5.4. | Basics about thermal management |
| 5.5.5. | Thermal challenges with chiplet design |
| 5.5.6. | Chiplet thermal management strategy |
| 5.5.7. | Key materials for packaging chiplet |
| 5.5.8. | Thermal interface materials |
| 5.5.9. | Strategies for semiconductor TIMs |
| 5.5.10. | TIM advancements |
| 5.5.11. | Heat sink material solutions |
| 5.5.12. | Optimizing heat sink design for advanced architectures |
| 5.5.13. | Other materials design consideration for thermal management |
| 5.5.14. | Material and process challenges in console failures |
| 5.5.15. | Warpage and solder joint issues |
| 5.5.16. | Cooling system for chips |
| 5.5.17. | Liquid cooling options |
| 5.5.18. | Design considerations for in-chip Cooling in 3D Chip stacks |
| 5.5.19. | Impingement cooling |
| 5.5.20. | Micro-heat pipes |
| 5.5.21. | TIM and cooling technologies limits |
| 5.6. | Others |
| 5.6.1. | Test access architecture |
| 5.6.2. | Testing for chiplets: |
| 5.6.3. | Chiplet testing |
| 5.6.4. | Different test techniques |
| 5.6.5. | Repair and redundancy |
| 5.6.6. | Antenna effect |
| 5.6.7. | Electromagnetic interference in chiplets |
| 6. | APPLICATION AREAS AND USE CASES |
| 6.1. | Chiplet for high performance computing chips |
| 6.2. | Chiplet use cases 1 |
| 6.3. | Chiplet use cases 2 |
| 6.4. | Marvell's Mochi |
| 6.5. | DARPA's work 1 |
| 6.6. | DARPA's work 2 |
| 6.7. | Chiplet architecture used in Apple chips |
| 6.8. | Apple's UltraFusion technology |
| 6.9. | Intel's contributions to chiplet |
| 6.10. | Intel's Ponte Vecchio |
| 6.11. | Intel's Agilex FPGAs |
| 6.12. | Intel Gaudi 3 |
| 6.13. | AMD's chiplet history |
| 6.14. | AMD's 1st generation EPYC |
| 6.15. | AMD's 2nd generation EPYC |
| 6.16. | AMD Chiplet cost |
| 6.17. | Genoa and MI300 |
| 6.18. | AMD's GPU based on chiplet design |
| 6.19. | Nvidia B200 |
| 6.20. | AWS Graviton 4 |
| 6.21. | Alphawave Semi's efforts |
| 6.22. | Ayar Labs' TeraPHY optical I/O chiplet |
| 6.23. | The first Chiplet Factory |
| 6.24. | Tenstorrent's chiplet technology |
| 6.25. | Eliyan's interconnects |
| 6.26. | Kiwi Moore's Kiwi SoChiplet Platform |
| 6.27. | Japanese automotive chiplet research group |
| 6.28. | European chiplet supply chain project |
| 6.29. | Imec's automotive chiplet initiative |