Co-Packaged Optics (CPO) 2026-2036: Technologies, Market, and Forecasts

CPO, optical interconnects, optical IO, data center, switches, AI, advanced semiconductor packaging, 2.5D, 3D, optical engine, EIC, PIC

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The rise of Co-Packaged Optics (CPO)
In recent years, optical transceiver technology has been steadily shifting toward placing the optics closer to the Application-Specific Integrated Circuit (ASIC). Traditionally, pluggable modules inserted into the front panel of a switch sit at the edge of the printed circuit board and have long served as the standard solution for connecting switches and servers in data centers. They remain popular for their flexibility, ease of replacement, and straightforward scaling. However, they face growing challenges, especially rising power consumption and limits on how much bandwidth can be delivered per unit of front panel area.
 
To address these constraints, the industry has begun migrating the optical engine closer to the switch ASIC in an effort to shorten the copper trace used for electrical signalling. Although these near packaged approaches improve electrical performance, they still diverge from the well-established pluggable ecosystem and key limitations remain. As a result, many in the industry expect the transition to progress directly toward fully integrated solutions such as co packaged optics.
 
IDTechEx's report titled "Co-Packaged Optics (CPO) 2026 to 2036: Technologies, Market, and Forecasts" examines this transition in detail. It reviews recent advances in CPO technology, tracks emerging packaging approaches, assesses the strategies of leading companies, and provides long term market forecasts. The report highlights how CPO adoption is set to reshape data center infrastructure in the coming decade.
Key trend of optical transceivers in high-end data center. Source: IDTechEx
 
The importance of advanced semiconductor packaging technologies for Co-Packaged Optics (CPO)
Traditional pluggable optical modules are increasingly constrained by signal loss, power consumption, and latency because they require long electrical traces between the switch ASIC and the optical engine. Co-packaged optics overcomes these limitations by placing the optical engine much closer to the switching silicon. Its success depends on advanced semiconductor packaging technologies that enable high-density integration of photonic and electronic ICs, along with the seamless attachment of optical engines to switch ASICs or XPUs. This requires a range of packaging approaches, including 2.5D interposers, Through Silicon Vias (TSV), fan-out wafer-level packaging, and more recently, 3D integration supported by hybrid bonding.
 
At GTC 2025, NVIDIA introduced two new networking switch platforms, Spectrum X Photonics and Quantum X Photonics, both built on co packaged optics. Central to these platforms is TSMC's System on Integrated Chips technology, which provides the 3D integration infrastructure for NVIDIA's design. The SoIC X variant, TSMC's advanced bumpless hybrid bonding process, enables vertical stacking of logic dies and other heterogeneous components at sub ten micrometer pitch. This dramatically shortens interconnect length and reduces resistance and latency.
 
Other major players, including Broadcom, have also adopted TSMC's COUPE platform, underscoring the growing importance of 3D integration and hybrid bonding in CPO.
 
Co-Packaged Optics (CPO) Market trajectory
According to IDTechEx, the Co-Packaged Optics (CPO) market is projected to exceed US$20 billion by 2036, growing at a robust CAGR of 37% from 2026 to 2036. CPO network switches are expected to dominate revenue generation, driven by each switch potentially incorporating up to 16 CPO PICs. Optical interconnects for AI system will constitute approximately 10% of the market, with each AI accelerator typically utilizing one optical interconnect PIC to meet increasing demands for high-speed data processing and communication in advanced computing applications.
 
IDTechEx's latest report, titled "Co-Packaged Optics (CPO) 2026-2036: Technologies, Market, and Forecasts," offers an extensive exploration into the latest advancements within co-packaged optics technology. The report delves deep into key technical innovations and packaging trends, providing a comprehensive analysis of the entire value chain. It thoroughly evaluates the activities of major industry players and delivers detailed market forecasts, projecting how the adoption of CPO will reshape the landscape of future data center architecture.
 
Central to the report is the recognition of advanced semiconductor packaging as the cornerstone of co-packaged optics technology. IDTechEx places significant emphasis on understanding the potential roles that various semiconductor packaging technologies may play within the realm of CPO.
 
Key aspects of the report include:
 
The report is based on extensive research and interviews with industry experts and provides valuable insights for anyone interested in gaining a strategic understanding of Co-Packaged Optics' role in advancing the future of data center and AI technology.
 
This report provides a comprehensive analysis of Co-Packaged Optics (CPO), encompassing various critical aspects:
 
  • Market Dynamics: Examination of key players such as Nvidia, Broadcom, Cisco, Ranovus, and Intel, and the forces shaping the CPO landscape.
  • Innovations in CPO Design: Exploration of advanced CPO designs and their implications for enhancing data center efficiency and shaping future architecture.
  • Semiconductor Packaging Breakthroughs: Insight into the latest advancements in semiconductor packaging, including 2.5D and 3D technologies, and their role in enabling CPO innovation.
  • Optical Engines: Analysis of the drivers behind CPO's performance and efficiency advantages.
  • CPO for AI Interconnects: Exploration of how optical I/O can address the limitations of copper connections in AI applications, improving efficiency, latency, and data rates.
  • CPO for Switches: Assessment of the potential 25% efficiency gains in high-performance network switches through CPO integration.
  • Challenges and Solutions: Critical review of obstacles to CPO adoption and strategies to overcome them.
  • Future Analysis: Predictions and insights into the next generation of CPO and its anticipated impact on the industry.
 
  • Market Forecasts-10-year Data Center Population Cumulative Forecast
  • 10-year AI Accelerator Unit Shipments Forecast
  • 10-year CPO Interconnect for AI (Optical I/O) Unit Shipments Forecast
  • 10-year CPO Interconnect for AI (Optical I/O) Market Revenue Forecast
  • 10-year CPO-enabled Network Switch Unit Shipments Forecast
  • 10-year CPO-enabled Network Switch Market Revenue Forecast
  • 10-year Total CPO Market Revenue Forecast
 
 
Report MetricsDetails
Historic Data2024 - 2025
CAGRThe Co-Packaged Optics (CPO) market is projected to exceed $20 billion by 2036, growing at a robust CAGR of 37% from 2026 to 2036.
Forecast Period2026 - 2036
Forecast UnitsVolume (units); Revenue ($)
Regions CoveredWorldwide
Segments CoveredNetwork Switches, Optical I/O, EIC/PIC integration by different integration methods
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1.EXECUTIVE SUMMARY
1.1.What does a modern high-performance AI data center look like?
1.2.Switches: Key components in a modern data center
1.3.Advancements in Switch IC Bandwidth and the Need for Co-Packaged Optics (CPO) Technology
1.4.Overview of key challenges in data center architectures
1.5.Key trend of optical transceiver in high-end data centers
1.6.Design decisions for CPO compared to Pluggables
1.7.What is an Optical Engine (OE)
1.8.Heterogeneous integration and Co-Packaged Optics (CPO)
1.9.Overview of interconnection technique in semiconductor packaging
1.10.Key CPO applications: Network switch and computing optical I/O
1.11.EIC/PIC integration by advanced interconnect technique
1.12.2D to 3D EIC/PIC integration options
1.13.Benchmark table of different packaging technologies for EIC/PIC
1.14.Examples of packaging a 3D optical engine with an IC
1.15.Three types of CPO + XPU/switch ASIC packaging structures
1.16.Challenges and future potential of CPO technology
1.17.Supply Chain Overview
1.18.NVIDIA vs Broadcom: Strategic Comparison in AI Infrastructure and CPO Technologies
1.19.CPO product benchmark: NVIDIA vs Broadcom
1.20.NVIDIA and Broadcom: Divergent CPO Ecosystems
1.21.Current AI system architecture
1.22.Future AI architecture (short to mid term) predicted by IDTechEx
1.23.Future AI architecture (long term) predicted by IDTechEx
1.24.Forecasting the AI accelerator Market: Changes From the previous Edition
1.25.Forecasts with table: Server boards, CPUs and GPUs/Accelerators
1.26.Optical I/O for AI interconnect CPO Forecast (units shipped)
1.27.Optical I/O for AI interconnect CPO Forecast (revenue/market size)
1.28.CPO network switches (L2 Switches) for AI accelerators forecast (units shipped)
1.29.CPO network switches (L2 Switches) for AI accelerators forecast (market size and revenue)
1.30.Total CPO market
1.31.Total CPO by different EIC/PIC integration technology (unit shipment, millions)
1.32.System integration of network switches (L2 Switches) for AI accelerators forecast by packaging technologies (unit shipped)
1.33.System integration of Optical I/O Forecast by packaging technologies (units shipped)
2.CHALLENGES AND SOLUTIONS FOR FUTURE AI SYSTEM
2.1.1.The rise and the challenges of LLM
2.1.2.What does a modern high-performance AI data center look like?
2.1.3.Closer look into NVIDIA's state-of-the-art AI system
2.1.4.Switches: Key components in modern data centers
2.2.Scale-up, Scale-out, and Scale-across network
2.2.1.Scale-up and Scale-Out
2.2.2.Overview: Scale-up, Scale-out, and Scale-across
2.3.Challenges in Network Switches Interconnect for High-end Data Centers
2.3.1.Roadmap of interconnect technology for network switches in high-end data centers
2.3.2.Serdes bottleneck in high-bandwidth systems
2.3.3.Solutions to Serdes bottlenecks in high-bandwidth systems
2.3.4.Pluggable optics - what are the bottlenecks?
2.3.5.On-Board Optics (OBO)
2.3.6.Co-Packaged Optics (CPO)
2.3.7.Transmission losses in a pluggable optical transceiver connection
2.3.8.Pluggable optics vs CPO
2.3.9.Design decisions for CPO compared to Pluggables
2.3.10.Advancements in switch IC bandwidth and the need for CPO technology
2.3.11.L2 frontside network architecture diagram CPO versus non-CPO
2.4.Challenges in Compute Switches Interconnect (i.e. Optical I/O) for High-end Data Centers
2.4.1.Number of Cu wires in current AI system Interconnects
2.4.2.Limitations in current copper systems in AI
2.4.3.Nvidia's connectivity choices: Copper vs optical for high-bandwidth systems
2.4.4.Copper vs. optical for high-bandwidth systems: Benchmark
2.4.5.Moving from Cu to optical interconnects for a high-end AI system
2.4.6.Current AI system architecture
2.4.7.L1 backside compute architecture with Cu systems
2.4.8.L1 backside compute architecture with optical interconnect: Co-Packaged Optics (CPO)
2.4.9.Opportunities for swapping copper interconnects to optical connects - what did the leader say?
2.5.Future AI system in high-end data center
2.5.1.Power efficiency comparison: CPO vs pluggable optics vs copper interconnects
2.5.2.Latency of 60cm data transmission technology benchmark
2.5.3.Future AI architecture (short to mid term) predicted by IDTechEx
2.5.4.Future AI architecture (long term) predicted by IDTechEx
3.INTRODUCTION TO CO-PACKAGED OPTICS (CPO)
3.1.1.What's covered in this chapter
3.2.PICs Key Concepts
3.2.1.What are Photonic Integrated Circuits (PICs)?
3.2.2.PICs vs Silicon Photonics - what are the differences
3.2.3.PIC architecture
3.2.4.Advantages and challenges of PIC
3.3.Optical Engine (OE)
3.3.1.What is an optical engine?
3.3.2.How an optical engine works
3.3.3.Optical power supplies
3.4.Co-Packaged Optics
3.4.1.Three key concepts in co-packaged optics (CPO)
3.4.2.Key technology building blocks for CPO
3.4.3.Benefits of CPO: Latency
3.4.4.Benefits of CPO: Power consumption
3.4.5.Benefits of CPO: Data rate
3.4.6.Overview of value proposition of CPO
3.4.7.Future challenges in CPO
4.PACKAGING FOR CO-PACKAGED OPTICS (CPO)
4.1.1.Key components to be packaged in an optical transceiver
4.1.2.Heterogeneous integration and Co-Packaged Photonics
4.1.3.CPO for network switch - packaging concept
4.1.4.Example: 1.6 Tbps Co-packaged optics for network switch
4.1.5.CPO as optical I/O for XPUs - packaging concept
4.1.6.CPO as optical I/O for XPUs - packaging concept (follow)
4.1.7.Example: CPO integration for compute silicon
4.1.8.Overview of CPO packaging technologies
4.2.Overview and development roadmap of 2.5D and 3D advanced semiconductor packaging technologies
4.2.1.Evolution roadmap of semiconductor packaging
4.2.2.Semiconductor packaging - an overview of technology
4.2.3.Key metrics for advanced semiconductor packaging performance
4.2.4.Overview of interconnection technique in semiconductor packaging
4.2.5.Overview of 2.5D packaging structure
4.3.2.5D Si-based Packaging Technologies
4.3.1.2.5D packaging that involves Si as interconnect
4.3.2.Through Si Via (TSV) - now and the future
4.3.3.Developing trend for 2.5D Si-based packaging
4.3.4.Si interposer vs Si bridge benchmark
4.4.2.5D Organic-based Packaging technologies
4.4.1.2.5D packaging - high density fan-out (FO) packaging
4.4.2.Redistribution Layer (RDL)
4.4.3.Electronic interconnects: SiO2 vs organic dielectric
4.4.4.Two types of fan-out: Panel level
4.4.5.Two types of fan-out: Wafer level
4.4.6.Wafer level fan-out vs panel level fan-out: The differences
4.4.7.Key trends in fan-out packaging
4.4.8.Challenges in future fan-out process
4.5.2.5D Glass-based Packaging Technologies
4.5.1.Roles of glass in semiconductor packaging
4.5.2.Glass core as interposer for advanced semiconductor packaging
4.5.3.Overcoming limitations of Si interposers with glass
4.5.4.Glass vs molding compound
4.5.5.Glass core (interposer) package - process flow
4.5.6.Challenges of glass packaging
4.6.3D Advanced Semiconductor Packaging Technologies
4.6.1.Evolution of bumping technologies
4.6.2.Challenges in scaling bumps
4.6.3.µ bump for advanced semiconductor packaging
4.6.4.Bumpless Cu-Cu hybrid bonding
4.6.5.Three ways of Cu-Cu hybrid bonding: Benchmark
4.6.6.Challenges in Cu-Cu hybrid bonding manufacturing process
4.7.CPO Packaging: EIC and PIC Integration
4.7.1.EIC/PIC integration - by conventional interconnect technique
4.7.2.EIC/PIC integration by emerging interconnect technique
4.7.3.2D to 3D EIC/PIC integration options
4.7.4.Benchmark table of different packaging technologies for EIC/PIC
4.7.5.Pros and Cons of 2D integration of EIC/PIC
4.7.6.Pros and Cons of 2.5D integration of EIC/PIC
4.7.7.Pros and Cons of 3D hybrid integration of EIC/PIC
4.7.8.Pros and Cons of 3D monolithic integration of EIC/PIC
4.8.TSV for EIC/PIC Integration
4.8.1.TSV for EIC/PIC integration in CPO
4.8.2.Why using TSV for PIC and EIC integration
4.8.3.Cisco packaging architectures of optical engine over generations
4.8.4.Cisco: 2.5D Chip-on-Chip (CoC) packaging architecture for EIC/PIC integration
4.8.5.Cisco: 3D TSV for PIC/EIC integration
4.8.6.Key TSV Fabrication steps and challenges in CPO - 1
4.8.7.Key TSV fabrication steps and challenges in CPO - 2
4.8.8.Packaging options for silicon photonics - w/ or w/o TSV?
4.8.9.Pros and Cons of 2.5D Si interposer for EIC/PIC integration
4.9.Fan-out for EIC/PIC Integration
4.9.1.ASE's proposed fan-out solution for CPO packaging
4.9.2.FOPOP from ASE - process
4.9.3.Detailed analysis of FOPOP vs WB packaging for CPO
4.9.4.Optical packaging process considerations for silicon photonics - ASE
4.9.5.SPIL's Fan-Out Embedded Bridge (FOEB) structure for PIC/EIC integration in CPO
4.9.6.Process flow of integrating PIC and EIC in a FOEB structure
4.9.7.Process challenges in packaging OE
4.9.8.Rockley Photonics proposes FOWLP for CPO packaging structure
4.9.9.Rockley Photonics' FOWLP CPO packaging process flow - 1
4.9.10.Rockley Photonics' FOWLP CPO packaging process flow - 2
4.9.11.Challenges of using fan-out for EIC/PIC integration
4.10.Glass-based CPO Packaging Technologies
4.10.1.Glass-based Co-packaged optics - Corning's vision
4.10.2.Glass-based Co-packaged optics - packaging structure
4.10.3.Glass-based Co-packaged optics - process development
4.10.4.Corning's 102.4 Tb/s test vehicle
4.11.Hybrid bonding for EIC/PIC integration
4.11.1.TSMC: Integrated HPC technology platform for AI
4.11.2.Optical engine roadmap from TSMC - 1
4.11.3.Optical engine roadmap from TSMC - 2
4.11.4.iOIS - Integrated Optical Interconnection System from TSMC
4.11.5.Combining EIC and PIC with 3D SoIC bond
4.11.6.Roadmap of bond pitch scaling
4.12.System integration of OE and ASIC/XPU, etc
4.12.1.Co-Packaging vs Co-Packaged Optics (CPO)
4.12.2.Three types of CPO + XPU/switch ASIC packaging structures
4.12.3.Examples of packaging an optical engine with an integrated circuit (IC) in a 2D or 2.5D configuration
4.12.4.OE integration with ASIC in a 2.5D configuration
4.12.5.Examples of packaging an optical engine with an integrated circuit (IC) in a 3D configuration
4.12.6.Future 3D-CPO structure
4.12.7.Nvidia's 3D integration of SoC, HBM, EIC and PIC on co-packaged substrates (TSV interposer)
4.12.8.Example of a 51.2 Tb/s switch module based on 3D integration of EIC/PIC
4.12.9.Process in fabrication of the 3D heterogeneous integration of EIC and PIC on a glass interposer
4.12.10.Example of a switch module based on 3D integration of EIC/PIC on glass interposer
4.12.11.Challenges and Future Potential of CPO Technology
4.13.Optical alignment and Laser Integration
4.13.1.How CPO is Built and the Bottleneck
4.13.2.Interface between Coupler and FAU - Key to the success of CPO packaging
4.13.3.Grating vs Edge Couplers: Challenges in high-density optical I/O for silicon photonics
4.14.Fiber Array Unit (FAU)
4.14.1.Optical alignment challenges and solutions - 1
4.14.2.Optical alignment challenges and solutions - 2
4.14.3.Optical alignment challenges and solutions - 3
4.14.4.Two alignment approaches
4.14.5.Reducing optical fiber packaging complexity
4.14.6.Key technical challenge: The size mismatch between silicon waveguides and planar optical fibers
4.14.7.Fiber Array Unit
4.14.8.Fiber Attach Methods
4.14.9.Key players in FAU for CPO
4.14.10.FOCI (Fiber Optical Communication Inc.)
4.14.11.FOCI's SiPh and CPO product roadmap
4.14.12.Baseline Optical Fiber Alignment Structure from FOCI
4.14.13.Benchmark of Optical Fiber Alignment Structure Variations - 1
4.14.14.Benchmark of Optical Fiber Alignment Structure Variations - 2
4.14.15.Benchmark of Optical Fiber Alignment Structure Variations - 3
4.14.16.Senko Advanced Components
4.14.17.Senko Advanced Components - Key CPO solution
4.14.18.Senko Advanced Components - Partnership
4.14.19.Suppliers of Other Optical Components in CPO (1)
4.14.20.Suppliers of Other Optical Components in CPO (2)
4.15.Laser Integration
4.15.1.On-chip light source integration methods
4.15.2.External lasers for CPO (1)
4.15.3.External lasers for CPO (2)
4.15.4.Laser attach technology benchmark - 1
4.15.5.Laser attach technology benchmark - 2
4.15.6.Benchmark of different laser integration technology
5.KEY CPO COMPANIES: DESIGN ROADMAP, STRATEGIES, ECOSYSTEM
5.1.Supply Chain Overview
5.2.Broadcom
5.3.Broadcom CPO Products Benchmark
5.4.Broadcom's CPO strategy
5.5.Advanced Semiconductor Packaging Approach for Broadcom's CPO
5.6.Broadcom's XPU-CPO
5.7.Detachable fiber connector
5.8.Broadcom's CPO roadmap
5.9.Broadcom CPO ecosystem
5.10.Nvidia: Opportunities for Co-Packaged Optics
5.11.Nvidia's CPO strategy
5.12.NVIDIA'S CPO: Spectrum-X and Quantum-X
5.13.NVIDIA'S CPO - Partnerships
5.14.Nvidia: Challenges and final thoughts for Co-Packaged Optics
5.15.Competition between Nvidia and Broadcom
5.16.NVIDIA vs Broadcom: Strategic Comparison in AI Infrastructure and CPO Technologies
5.17.CPO product benchmark: NVIDIA vs Broadcom
5.18.NVIDIA and Broadcom: Divergent CPO Ecosystems
5.19.Marvell
5.20.Marvell's XPU-CPO
5.21.Marvell's CPO reference design
5.22.Ranovus products and progress - (1)
5.23.Ranovus products and progress - (2)
5.24.Ranovus Partnerships
5.25.MediaTek - CPO strategy/Roadmap/Partnership
5.26.Lightmatter
5.27.Lightmatter M1000
5.28.Lightmatter - Passage ™: 3D Photonic Interposer (1)
5.29.Lightmatter - Passage ™: 3D Photonic Interposer (2)
5.30.Lightmatter: L-Series (3D CPO)
5.31.Lightmatter: Partners
5.32.Ayar Labs TeraPHY
5.33.Ayar Labs Recent Collaboration for AI scale-up - 1
5.34.Ayar Labs Recent Collaboration for AI scale-up - 2
5.35.Cisco Co-Packaged Optics demo
5.36.Cisco: CPO power efficiency
5.37.Cisco: External lasers (ELFPP)
5.38.Intel Optical Compute interconnect
5.39.Intel Optical Compute interconnect (2)
6.MARKET FORECASTS
6.1.Forecasting the AI accelerator Market: Changes From the previous Edition
6.2.Forecasting Growth in GPUs and Other Accelerators
6.3.Forecasts with table: Server boards, CPUs and GPUs/Accelerators
6.4.Optical I/O for AI interconnect CPO Forecast (units shipped)
6.5.Optical I/O for AI interconnect CPO Forecast (revenue/market size)
6.6.CPO network switches (L2 Switches) for AI accelerators forecast (units shipped)
6.7.CPO network switches (L2 Switches) for AI accelerators data table (units shipped)
6.8.CPO network switches (L2 Switches) for AI accelerators forecast (market size and revenue)
6.9.Total CPO market
6.10.Total CPO by different EIC/PIC integration technology (unit shipment, millions)
6.11.System integration of network switches (L2 Switches) for AI accelerators forecast by packaging technologies (unit shipped)
6.12.System integration of Optical I/O Forecast by packaging technologies (units shipped)
6.13.Table for CPO unit forecast by packaging technologies
7.COMPANY PROFILES
7.1.ACCRETECH (Grinding Tool)
7.2.AEPONYX
7.3.Amkor — Advanced Semiconductor Packaging
7.4.ASE — Advanced Semiconductor Packaging
7.5.Ayar Labs: AI Accelerator Interconnect
7.6.CEA-Leti (Advanced Semiconductor Packaging)
7.7.Coherent: Photonic Integrated Circuit-Based Transceivers
7.8.EFFECT Photonics
7.9.EVG (3D Hybrid Bonding Tool)
7.10.GlobalFoundries
7.11.HD Microsystems
7.12.Henkel (Semiconductor packaging, Adhesive Technologies division)
7.13.iPronics: Programmable Photonic Integrated Circuits
7.14.JCET Group
7.15.JSR Corporation
7.16.Lightelligence
7.17.Lightmatter
7.18.LioniX
7.19.LIPAC
7.20.LPKF
7.21.Mitsui Mining & Smelting (Advanced Semiconductor Packaging)
7.22.NanoWired
7.23.Resonac (RDL Insulation Layer)
7.24.Scintil Photonics
7.25.TOK
7.26.TSMC (Advanced Semiconductor Packaging)
7.27.Vitron (Through-Glass Via Manufacturing) — A LPKF Trademark
 

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Ordering Information

Co-Packaged Optics (CPO) 2026-2036: Technologies, Market, and Forecasts

£€$元¥₩
Electronic (1-5 users)
£5,650.00
Electronic (6-10 users)
£8,050.00
Electronic and 1 Hardcopy (1-5 users)
£6,450.00
Electronic and 1 Hardcopy (6-10 users)
£8,850.00
Electronic (1-5 users)
€6,400.00
Electronic (6-10 users)
€9,200.00
Electronic and 1 Hardcopy (1-5 users)
€7,400.00
Electronic and 1 Hardcopy (6-10 users)
€10,200.00
Electronic (1-5 users)
$7,500.00
Electronic (6-10 users)
$10,750.00
Electronic and 1 Hardcopy (1-5 users)
$8,600.00
Electronic and 1 Hardcopy (6-10 users)
$11,850.00
Electronic (1-5 users)
元54,000.00
Electronic (6-10 users)
元76,000.00
Electronic and 1 Hardcopy (1-5 users)
元61,000.00
Electronic and 1 Hardcopy (6-10 users)
元84,000.00
Electronic (1-5 users)
¥990,000
Electronic (6-10 users)
¥1,406,000
Electronic and 1 Hardcopy (1-5 users)
¥1,140,000
Electronic and 1 Hardcopy (6-10 users)
¥1,556,000
Electronic (1-5 users)
₩10,500,000
Electronic (6-10 users)
₩15,000,000
Electronic and 1 Hardcopy (1-5 users)
₩12,100,000
Electronic and 1 Hardcopy (6-10 users)
₩16,600,000
Click here to enquire about additional licenses.
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The total CPO market is set to exceed US$20 billion by 2036, growing at a robust CAGR of 37%
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Report Statistics

Slides 290
Forecasts to 2036
Published Dec 2025
 

Preview Content

pdf Document Sample pages
 

Customer Testimonial

quote graphic
"The resources produced by IDTechEx are a valuable tool... Their insights and analyses provide a strong foundation for making informed, evidence-based decisions. By using their expertise, we are better positioned to align our strategies with emerging opportunities."
Director of Market Strategy
Centre for Process Innovation (CPI)
 
 
 
ISBN: 9781835701591

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