1. | EXECUTIVE SUMMARY |
1.1. | Evolution roadmap of semiconductor packaging |
1.2. | Comparison Table of 2.5D and 3D IC Integration in HPC chips |
1.3. | Power Challenges in Advanced Semiconductor Packaging for HPC chips |
1.4. | Overview of Power Management Components for HPC chips |
1.5. | Impact of Key Design Parameters on PDN Performance in 2.5D Integration |
1.6. | Challenges of Power Delivery in 3DICs |
1.7. | Thermal Challenges in 3DICs |
1.8. | Backside Power Delivery for Next Generation HPC chips |
1.9. | Overview of Critical Thermal Challenges in BSPDN: Hotspots, Cooling, and Materials |
1.10. | Design and Process Considerations for TSV Reliability in Advanced Packaging |
1.11. | Key Process Factors Affecting TSV Electrical Performance |
1.12. | Moving from Lateral Power Delivery (LPD) to Vertical Power Delivery (VPD) |
1.13. | Tomorrow's CoWoS: Toward Functional Interposers |
1.14. | TIM1 Considerations |
1.15. | Potential TIM1 options in the future |
1.16. | Diamond as substrate materials - challenges |
1.17. | Benchmark Cooling Technologies for HPC |
1.18. | Transition towards microfluidic cooling - ultimate approach |
1.19. | Overview of Cooling Strategies for High-Power 2.5D/3D Packages - 1 |
1.20. | Overview of Cooling Strategies for High-Power 2.5D/3D Packages - 2 |
1.21. | Market share forecast of TIM1 and TIM1.5 for ASP forecast by type: 2026-2036 (area based) |
1.22. | TIM1 and TIM1.5 area forecast for ASP: 2026-2036 |
1.23. | TIM1 and TIM1.5 market size forecast for ASP: 2026-2036 |
1.24. | Market share forecast of TIM1 and TIM1.5 for ASP forecast by type: 2026-2036 (market size based) |
1.25. | Microfluidic cooling ASP unit forecast: 2026-2036 |
1.26. | Access More With an IDTechEx Subscription |
2. | INTRODUCTION |
2.1. | Thermal design power (TDP) |
2.2. | 10-Year TDP Trends for HPC (High Performance Computing) Chips |
2.3. | Key Factors Driving the Rise in TDP for HPC chips |
2.4. | Evolution roadmap of semiconductor packaging |
2.5. | 2.5D vs 3D IC Advanced Semiconductor Packaging Technologies in HPC chips |
2.6. | Comparison Table of 2.5D and 3D IC Integration in HPC chips |
2.7. | Thermal Characteristics and Challenges of 2.5D/3D Packages |
2.8. | Thermal Benefits of Advanced Semiconductor Packaging in HPC Chips |
2.9. | Why 2.5D Packaging Technologies Dominates Today's High-End HPC chips |
2.10. | Summary of TDP Implications in Advanced Packaging |
2.11. | Real-World Examples of 2.5D and 3D Packaging in GPUs |
2.12. | Overview of Cooling Strategies for High-Power 2.5D/3D Packages - 1 |
2.13. | Overview of Cooling Strategies for High-Power 2.5D/3D Packages - 2 |
3. | OVERVIEW AND DEVELOPMENT ROADMAP OF 2.5D AND 3D ADVANCED SEMICONDUCTOR PACKAGING TECHNOLOGIES |
3.1. | Evolution roadmap of semiconductor packaging |
3.2. | Semiconductor packaging - an overview of technology |
3.3. | Key metrics for advanced semiconductor packaging performance |
3.4. | Overview of interconnection technique in semiconductor packaging |
3.5. | Overview of 2.5D packaging structure |
3.6. | Evolution of bumping technologies |
3.7. | Challenges in scaling bumps |
3.8. | µ bump for advanced semiconductor packaging |
3.9. | Bumpless Cu-Cu hybrid bonding |
4. | POWER MANAGEMENT IN 2.5D AND 3DIC |
4.1.1. | Chapter Introduction |
4.2. | Introduction to Power Delivery in in Advanced Semiconductor Packaging for HPC |
4.2.1. | Power Challenges in Advanced Semiconductor Packaging for HPC chips |
4.2.2. | Overview of Power Management Components for HPC chips |
4.2.3. | Advanced Power Delivery Networks (PDNs) |
4.2.4. | Key Power Supply Noise (PSN) Metric that Affects PDN Performance |
4.2.5. | Dynamic Voltage and Frequency Scaling (DVFS) |
4.2.6. | Power Gating |
4.2.7. | Clock Gating |
4.2.8. | Thermal Management Runtime Loops |
4.2.9. | On-Package Voltage Regulation (OPVR) |
4.2.10. | Decoupling Capacitors (Decaps) |
4.2.11. | Low-Resistance Interconnects |
4.3. | Power Delivery Network (PDN) Evaluation of 2.5D |
4.3.1. | Power Delivery Network Evaluation of 2.5D Interposer Integration Platforms |
4.3.2. | Power Delivery Network Evaluation of 2.5D Bridge Integration Platforms |
4.3.3. | Including PDN in 2.5D bridge-chip |
4.3.4. | Impact of include P/G Networks in Bridge-chip PDN |
4.3.5. | Add Decoupling Capacitors in 2.5D Bridge |
4.3.6. | Decap Overdesign and Trade-offs |
4.3.7. | Impact of Bridge-Chip Size and Capacitance Density Trade-Off |
4.3.8. | Impact of Key Design Parameters on PDN Performance in 2.5D Integration |
4.3.9. | TSV impact on PDN performance |
4.3.10. | Bump Pitch Impact on PDN performance |
4.4. | Power Delivery Network (PDN) Evaluation of 3D |
4.4.1. | Overview of the Rise of 3DICs |
4.4.2. | Challenges of Power Delivery in 3DICs - (1) |
4.4.3. | Challenges of Power Delivery in 3DICs - (2) |
4.4.4. | Thermal Challenges in 3DICs |
4.4.5. | Advanced 3DIC Integration Trend |
4.4.6. | Backside Power Delivery Network (BSPDN) - 1 |
4.4.7. | Backside Power Delivery Network (BSPDN) - 2 |
4.4.8. | Three Main BPD Architectures |
4.4.9. | Buried Power Rails (BPRs) |
4.4.10. | How BSPDN Affects Thermal Behavior - imec study |
4.4.11. | Overview of Critical Thermal Challenges in BSPDN: Hotspots, Cooling, and Materials |
4.4.12. | BSPDN Thermal Optimization Strategies |
4.4.13. | Summary of BSPDN Benefits, Challenges, and Thermal Implications in 3DICs |
4.4.14. | Through Si Via (TSV) |
4.4.15. | TSV fabrication process |
4.4.16. | TSV in 3DIC |
4.4.17. | Example: Wafer-Level F2B Cu-Cu Hybrid Bonding with High-Density TSVs for 3D Integration |
4.4.18. | Design and Process Considerations for TSV Reliability in Advanced Packaging |
4.4.19. | Key Process Factors Affecting TSV Electrical Performance |
4.4.20. | TSV Scaling Trend |
4.4.21. | Thermal Modeling and Impact of TSVs in 3D IC Integration |
4.5. | Case studies from Industry Players |
4.5.1. | TSMC: CoWoS-L key development features |
4.5.2. | TSMC CoWoS-L for the next generation AI chips |
4.5.3. | Deep Trench Capacitor (DTC) vs Traditional Capacitors |
4.5.4. | Deep Trench Capacitor (DTC) for 3DIC - 1 |
4.5.5. | Deep Trench Capacitor (DTC) for 3DIC - 2 |
4.5.6. | Tomorrow's CoWoS: Toward Functional Interposers |
4.5.7. | Technical Challenges Associated with IVR Integration in Interposers |
4.5.8. | SPIL's advanced 2.5D solution: FOEB-T |
4.5.9. | SPIL Performance benchmark: FOEB vs FOEB-T vs 2.5D Si interposer |
4.5.10. | ASE: PowerSiP™ platform for power hungry HPC system |
4.5.11. | ASE: FOCoS-B (w/ and w/o TSVs) Examples and Spec |
4.5.12. | Samsung: 2.5D packaging solutions (I-Cube) |
4.6. | Moving from Lateral Power Delivery (LPD) to Vertical Power Delivery (VPD) |
4.7. | Existing Voltage Regulator Technologies |
4.8. | Improve Thermal in SRAM-on-Logic 3D packaging |
4.9. | Thermal Behavior and Heat Sink Optimization in Advanced 3D Packaging |
4.10. | Thermal Stability Comparison of PCM vs Thermal Grease for Large-Size 2.5D Packaging |
5. | NOVEL THERMAL MATERIALS AND SOLUTIONS FOR ADVANCED PACKAGING |
5.1. | Introduction |
5.1.1. | Trend Towards 3D Packaging and Advanced Thermal Management |
5.1.2. | Die-Attach for CPUs, GPUs and Memory Modules |
5.1.3. | Trends of TIM1 in 3D Semiconductor Packaging |
5.1.4. | Die Attach Materials Comparison |
5.1.5. | Where Are TIM1 Used |
5.1.6. | TIM1 Considerations |
5.1.7. | Liquid Cooling Options |
5.2. | Thermal interface materials |
5.2.1. | Thermal interface material inside the packaging - TIM1 |
5.2.2. | Potential TIM1 options in the future |
5.2.3. | Indium foil TIM1 - issues with multiple reflow process |
5.2.4. | Traditional and mature product - Shin-Estu X-23 series for BGA |
5.2.5. | Thermal Gel - Shin-Etsu MicroSi |
5.2.6. | Silver-filled thermal grease - potential solution for FCBGA |
5.2.7. | Graphene - proved uses as TIM1.5 and Resonac's Graphene has been used as TIM1 |
5.2.8. | Graphene - bare die + TIM1.5 most popular method with wrapping process |
5.2.9. | Liquid metal - TIM1 or TIM1.5 for 2.5D packaging |
5.2.10. | Challenges of liquid metals and solution of using solid/liquid approach from Indium Corp |
5.2.11. | Indium Corp - liquid metal |
5.2.12. | Yunnan Zhongxuan Liquid Metal Technology Co., Ltd. |
5.2.13. | Yunnan Zhongxuan - helping with establishing the industry standard of liquid metal |
5.2.14. | Liquid metals for servers - Nvidia 5090 |
5.2.15. | Thermally conductive sheet using vertical oriented graphite fillers as TIM1 |
5.2.16. | Resonac TIMs |
5.2.17. | Arieca - liquid metal embedded elastomer (LMEEs) |
5.2.18. | Arieca - LMEEs Test |
5.2.19. | Diamond as TIM0 to avoid hotspots - early research stage |
5.2.20. | Integrated Si Micro-Cooler with liquid metal and SiOx TIM |
5.2.21. | Chip and package level - CuNWs/PDMS based TIMs |
5.2.22. | Liquid CuNW infused nanostructured composite as TIM (1/2) |
5.2.23. | Liquid CuNW infused nanostructured composite as TIM (2/2) |
5.3. | Diamond usage in ASP |
5.3.1. | Cu/Diamond substrate - small-scale testing |
5.3.2. | Challenges of diamond/Cu substrate |
5.3.3. | Diamond heat sink cooling solution for 3D packaging |
5.3.4. | Cu/diamond fabrication - cold spraying |
5.3.5. | Thermally-enhanced micro-bump with embedded metal structure |
5.3.6. | Interdiffusion Cu-Cu bonds to enable a higher thermal conductance |
5.3.7. | Diamond-on-chip-on-glass interposer for efficient thermal management |
5.3.8. | Diamond interposer - investigation of heat dissipation |
5.3.9. | Diamond as substrate - single-crystal or polycrystalline? |
5.3.10. | Diamond as substrate materials - challenges |
6. | LIQUID COOLING |
6.1. | Overview |
6.1.1. | Liquid Cooling and Immersion Cooling |
6.1.2. | Comparison of Liquid Cooling Technologies (1) |
6.1.3. | Comparison of Liquid Cooling Technologies (2) |
6.1.4. | Liquid Cooling - Power Limitation of Different Cooling on Rack Level |
6.1.5. | Different Cooling on Chip Level |
6.1.6. | Cooling Technology Comparison |
6.2. | Direct-to-chip (D2C) cooling |
6.2.1. | Liquid Cooling Cold Plates |
6.2.2. | Benefits and Drawbacks of Cold Plate Cooling |
6.2.3. | Thermal Cost Analysis of Cold Plate System - (1) |
6.2.4. | Thermal Cost Analysis of Cold Plate System - (2) |
6.2.5. | Single-Phase Cold Plate |
6.2.6. | Single-Phase Cold Plate Considerations |
6.2.7. | Why Single-Phase Cold Plate Might Dominate |
6.3. | Immersion Cooling |
6.3.1. | Single-Phase and Two-Phase Immersion - Overview (1) |
6.3.2. | Single-Phase Immersion Cooling (2) |
6.3.3. | SWOT: Single-Phase Immersion Cooling |
6.3.4. | Overview: Two-Phase Immersion Cooling |
6.3.5. | SWOT: Two-Phase Immersion Cooling |
6.3.6. | Roadmap of Single-Phase Immersion Cooling |
6.3.7. | Roadmap of Two-Phase Immersion Cooling |
6.4. | Microfluidic cooling |
6.4.1. | Benchmark Cooling Technologies for HPC |
6.4.2. | Microfluidic Overview |
6.4.3. | Benchmark of Cooling Configurations for HPC Packages |
6.4.4. | Microchannel studies - performance benchmark |
6.4.5. | Design Principles and Challenges of Microchannel Heat Sink Architecture - 1 |
6.4.6. | Design Principles and Challenges of Microchannel Heat Sink Architecture - 2 |
6.4.7. | Wafer-Level Microchannel Integration for Cooling |
6.4.8. | Thermal Design Considerations and Coolant Selection for Microchannel Systems |
6.4.9. | Barriers to Microchannel Integration and System Adoption |
6.4.10. | Microsoft - Integrated Silicon Microfluidic Cooling |
6.4.11. | Microfluidics Cooling Heatsink Structure and Manufacture |
6.4.12. | On-package liquid cooling for HPC |
6.4.13. | imec - microfluidic cooling (1/2) |
6.4.14. | imec - microfluidic cooling (2/2) |
6.4.15. | Intel foundry thermal capabilities with TIM options and in-package liquid cooling |
6.4.16. | IBM z17 |
7. | FORECASTS |
7.1. | Assumptions of the variables for TIMs |
7.2. | Trend of planar die packaging area for GPUs |
7.3. | CoWoS - development progress and roadmap |
7.4. | Market share forecast of TIM1 and TIM1.5 for ASP forecast by type: 2026-2036 (area based) |
7.5. | TIM1 and TIM1.5 area forecast for ASP: 2026-2036 |
7.6. | TIM1 and TIM1.5 Considerations |
7.7. | TIM1 and TIM1.5 market size forecast for ASP: 2026-2036 |
7.8. | Market share forecast of TIM1 and TIM1.5 for ASP forecast by type: 2026-2036 (market size based) |
7.9. | Microfluidic cooling ASP unit forecast: 2026-2036 |
7.10. | Liquid cooling for data center forecast (D2C and Immersion): 2025-2035 |
8. | PROFILES |
8.1. | Accelsius — Two-Phase Direct-to-Chip Cooling |
8.2. | Amkor — Advanced Semiconductor Packaging |
8.3. | Arieca |
8.4. | ASE — Advanced Semiconductor Packaging |
8.5. | Asperitas Immersed Computing |
8.6. | Carbice |
8.7. | Green Revolution Cooling (GRC) |
8.8. | LiquidCool Solutions — Chassis-Based Immersion Cooling |
8.9. | Resonac Holdings Corporation: Liquid Crystal Acryl Elastomer (LCE) |
8.10. | Samsung Electronics (Memory) |
8.11. | Shenzhen HFC |
8.12. | Smart High Tech and Shanghai Ruixi |
8.13. | Sumitomo Chemical Co., Ltd |
8.14. | TSMC (Advanced Semiconductor Packaging) |
8.15. | ZutaCore |