Prof Kos Galatsis, Co-Founder
Apr 04, 2012.
• High mobility, low temperature CNT backplane solutions for mobile display applications.
• Pathway to high yield ink-jet printed electronics.
• Benchmark comparison to LTPS, a-Si and metal oxide semiconductor backplane solutions.
• Low power, high mobility, fully printed CNT backplane transistor demonstration.
Speaker Biography (Kos Galatsis)
Kos Galatsis is an Associate Professor with the Material Science and Engineering Department at UCLA and co-founder of Aneeve Nanotechnologies. His research interests include nanoelectronics, novel emerging logic and memory devices, alternate state variables, printed electronics and carbon based devices. On behalf of the semiconductor industry he manages Centers of Excellence in nanoelectronics with project portfolios of over $10M per year in the areas of emerging memory, logic and architectures and patterning technologies. Dr. Galatsis has published over 5 book chapters, involved in 7 patents applications and published over 50 referred journal papers. He is a contributor to International Technology Roadmap for Semiconductors (ITRS) chapter on Emerging Research Devices and Materials chapters and is the 2012 Chairman of the International Planning Working Group for Nanoelectronics (IPWGN).
Company Profile (Aneeve Nanotechnologies)
View Aneeve Nanotechnologies Timeline
Aneeve Nanotechnologies is a startup company spun-out of UCLA and currently in the California NanoSystems Institute (CNSI). Aneeve's mission is to develop low cost low-power-consuming nanotechnology-based electronics for wireless and mobile device applications. Aneeve has developed a fully printed high mobility and high yield backplane printing technology leveraging the superior transport properties of semiconducting carbon nanotubes that go beyond state-of-the-art LTPS, a-Si and oxide semiconductor backplane options.