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先端半導体パッケージングの材料とプロセス 2024-2034年

2.5D、3D、先端半導体パッケージング、RDL、誘電体材料、Cu-Cuハイブリッド接合、EMC、MUF

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製品情報 概要 目次 FAQ (よくある質問) 価格 Related Content
この包括的な調査レポートは、この分野のIDTechExの広範にわたる知識と経験に基づき、先端半導体パッケージングで使用される材料や加工技術に関する重要な知見を提供しています。また、2.5Dパッケージングプロセスフローや3Dパッケージングの革新的Cu-Cuハイブリッドボンディング技術を含む、重要な技術トレンドを網羅しています。これに加え、本レポートは、Organic Dielectric Advanced Semiconductor Packaging Moduleの10年間市場予測を提供します。
「先端半導体パッケージングの材料とプロセス 2024-2034年」が対象とする主なコンテンツ
（詳細は目次のページでご確認ください）
● 第1章: 概要と結論
● 第2章: 先端半導体パッケージング（ASP）のイントロダクション
● 第3章: 先端半導体パッケージング: パフォーマンス評価、製造プロセス、材料へのリンク
□ 2.5Dパッケージング・プロセスフローのノウハウ
□ 第3.2章 再配線層（RDL）とマイクロビア（材料）
□ 第3.3章 再配線層（RDL）とマイクロビア（製造プロセス）
□ 第3.4章 エポキシ樹脂封止材（EMC）とモールドアンダーフィル材（MUF）
● 第4章 3Dダイスタッキング向けCu-Cuハイブリッド接合技術
□ Cu-Cuハイブリッド接合（製造プロセス）
□ Cu-Cuハイブリッド接合（材料選定）
□ 有機絶縁膜によるCu-Cuハイブリッド接合（事例検証）
□ 無機絶縁膜によるCu-Cuハイブリッド接合（事例検証）
● 第5章: 市場予測
 
Why do we need Advanced Semiconductor Packaging?
We are living in a data-centric world. The growing amount of data generated in various industries is increasingly driving the demand for high-bandwidth computing. Applications such as machine learning and AI require powerful processing capabilities, leading to the need for dense transistor placement on chips and compact interconnection bump pitches in packaging. The latter highlights the significance of semiconductor technologies in meeting these requirements.
 
Semiconductor packaging has evolved from board-level to wafer-level integration, bringing notable advancements. Wafer level integration provides advantages over traditional methods, such as increased connection density, smaller footprints for size-sensitive applications, and enhanced performance.
 
"Advanced" semiconductor packaging specifically includes high-density fan-out, 2.5D, and 3D packaging, characterized by a bumping pitch size below 100 µm, enabling at least 10x higher interconnect densities.
 
Bandwidth is key
To enhance bandwidth from a packaging perspective, two key factors come into play: the total number of I/Os (input/output) and the bit rate per I/O. Increasing the total number of I/Os requires enabling finer line/space (L/S) patterns in each routing layer/redistribution layer (RDL) and having a higher number of routing layers. On the other hand, improving the bit rate per I/O is influenced by the interconnect distance between chiplets and the selection of dielectric materials. These factors directly impact the overall performance and efficiency of the packaging system.
 
Key factors that affect the bandwidth of a packaged module. Source: IDTechEx
 
Unleashing High Bandwidth: Exploring Materials and Processing for Advanced Semiconductor Packaging
Delving deeper into achieving higher wiring density and a higher bit rate per I/O from a materials and processing perspective reveals the critical role played by the selection of dielectric materials and the utilization of appropriate processing techniques. These factors have a significant impact on the overall performance and capabilities of the packaging system.
 
Electronic interconnects: SiO2 vs Organic dielectric. Source: IDTechEx
 
Selecting suitable dielectric materials is crucial, considering properties like low dielectric constant, optimal CTE (as close to the CTE of Cu as possible), and favorable mechanical characteristics that ensure module reliability, such as Young's modulus and elongation. These choices enable higher data rates while preserving signal integrity and facilitating fine line/space features for increased wiring density.
 
In high-performance accelerators, such as GPUs, inorganic dielectrics like SiO2 have been extensively utilized to achieve ultra-fine line/space (L/S) features. Nevertheless, their use is limited in applications that demand high-speed connectivity due to their high RC delays. As an alternative, organic dielectrics have been proposed for their cost-effectiveness and ability to mitigate RC delays through their low dielectric constant. However, organic dielectrics present challenges, including high CTE, which can negatively impact the device reliability, and difficulties in scaling to fine L/S features.
 
In addition to selecting appropriate materials, the processing techniques employed during packaging fabrication play a crucial role in achieving a higher number of I/Os and improving the bit rate per I/O. The steps involved in 2.5D packaging processes, including lithography, CMP (Chemical Mechanical Planarization), etching processes, and the CMP and bonding processes in 3D Cu-Cu hybrid bonding, present challenges in achieving tighter routing and increased wiring density. IDTechEx provides detailed insights into how the choice of materials influences the fabrication processes, offering a comprehensive understanding of their impact on advanced semiconductor packaging.
 
What materials and technologies are covered in this report?
 
Scope of "Materials and Processing for Advanced Semiconductor Packaging 2024-2034". Source: IDTechEx
 
IDTechEx's "Materials and Processing for Advanced Semiconductor Packaging 2024-2034" report is divided into four main parts, offering a structured approach to understanding advanced semiconductor packaging. The first part provides a comprehensive introduction to the technologies, development trends, key applications, and ecosystem of advanced semiconductor packaging, providing readers with a solid overview knowledge. The second part focuses on 2.5D packaging processes, delving into crucial aspects including dielectric materials for RDL and Microvia, RDL fabrication techniques, and material selection for EMC and MUF. Each sub-section within this part presents a detailed analysis of process flows, technology benchmarks, player evaluations, and future trends, providing readers with comprehensive insights.
 
The report continues beyond the discussion of 2.5D packaging to the third part, which focuses on the innovative Cu-Cu hybrid bonding technology for 3D die stacking. This section provides valuable insights into the manufacturing process and offers guidance on material selection for optimal outcomes. It also showcases case studies highlighting the successful implementation of Cu-Cu hybrid bonding using both organic and inorganic dielectrics. Additionally, the report includes a 10-year market forecast for the Organic Dielectric Advanced Semiconductor Packaging Module, presented in the last chapter. This forecast encompasses unit and area metrics, providing industry with meaningful perspectives into anticipated market growth and trends for the next decade.
Report MetricsDetails
Historic Data2022 - 2023
Forecast Period2024 - 2034
Forecast UnitsVolume (units); mm2
Regions CoveredWorldwide
Segments CoveredOrganic Dielectric Advanced Semiconductor Packaging Module Area (Unit and mm2)
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詳細
この調査レポートに関してのご質問は、下記担当までご連絡ください。

アイディーテックエックス株式会社 (IDTechEx日本法人)
担当: 村越美和子 m.murakoshi@idtechex.com
1.EXECUTIVE SUMMARY AND CONCLUSIONS
1.1.Report scope
1.2.Advanced semiconductor packaging - An overview
1.3.From 1D to 3D semiconductor packaging
1.4.Semiconductor packaging - An overview of technology
1.5.Overview of interconnection technique in advanced semiconductor packaging
1.6.Key trends in fan-out packaging
1.7.Key factors to consider when choosing material for electronic interconnects
1.8.Key parameters for organic RDL materials for next generation 2.5D fan-out packaging
1.9.Benchmark of organic dielectrics for RDL
1.10.Industry players of organic RDL
1.11.Comparison of polymer dielectric materials in current high-performance packages
1.12.Benchmark of RDL formation technology
1.13.Overview of RDL L/S range by different RDL formation technology (1)
1.14.Overview of via diameter range by different microvia creation technology (1)
1.15.Overview of via diameter range by different microvia creation technology (2)
1.16.Overview of lithography challenges in high density RDL packaging
1.17.Key parameters for EMC materials
1.18.Challenges in conventional bumping
1.19.Micro bumps (µ bumps) vs bumpless Cu-Cu hybrid bonding
1.20.Overview of devices that make use of hybrid bonding
1.21.Cu-Cu hybrid bonding manufacturing process flow
1.22.3D SoIC process flow deep dive - 1
1.23.Key factors in hybrid bonding that are impacted by the choice of dielectric material
1.24.Inorganic dielectric vs organic dielectric: A quick overview
1.25.Technology Benchmark of different dielectric materials for Cu-Cu hybrid bonding
1.26.Key process know-how for inorganic dielectric Cu-Cu hybrid bonding
1.27.Comparison of polymer case studies for hybrid bonding benchmarking
1.28.Key summary of polymer dielectric for hybrid bonding research
1.29.Forecast: Organic Dielectric Advanced Semiconductor Packaging Module Area (Unit and mm2)
2.INTRODUCTION OF ADVANCED SEMICONDUCTOR PACKAGING
2.1.1.Advanced semiconductor packaging - An overview
2.1.2.The rise of advanced semiconductor packaging and its challenges
2.1.3.From 1D to 3D semiconductor packaging
2.1.4.Semiconductor packaging - An overview of technology
2.1.5.Overview of interconnection technique in advanced semiconductor packaging
2.1.6.Fan out wafer level packaging
2.1.7.Interposer technology
2.1.8.2.5D and 3D IC packaging
2.1.9.2.5D IC Packaging
2.1.10.2.5D IC packaging
2.1.11.3D IC packaging technology
2.1.12.3D IC packaging
2.1.13.3D IC packaging
2.1.14.Advanced semiconductor packaging technologies - Our scope
2.1.15.Packaging trend for key markets
2.2.Advanced Semiconductor Packaging - Ecosystem
2.2.1.Business value chain in the IC industry
2.2.2.Ecosystem/Business model in the IC industry
2.2.3.Role and advantages of players in advanced semiconductor packaging market
2.2.4.Players in advanced semiconductor packaging and their solutions
2.2.5.An overview of chip supply chain
3.ADVANCED SEMICONDUCTOR PACKAGING: PERFORMANCE EVALUATION, AND ITS LINK TO FABRICATION PROCESSES AND MATERIALS
3.1.1.Key factors impacting advanced semiconductor packaging performance
3.1.2.Primary considerations for advanced packaging
3.1.3.The key metrics that impact advanced semiconductor packaging performance: Bandwidth
3.1.4.The definition of IO density
3.1.5.IO density calculation
3.1.6.Routes to increase I/O density
3.1.7.The key metrics that impact advanced semiconductor packaging performance: Power efficiency
3.2.2.5D Packaging process flow know-how
3.2.1.2.5D Packaging - High density fan-out packaging
3.2.2.Key trends in fan-out packaging
3.2.3.Fan-out packaging process overview
3.2.4.Fan-out chip-first process flow
3.2.5.Fan-out Chip-last process flow
3.2.6.Fan-out chip last RDL formation - Development trend
3.2.7.Challenges in future fan-out process
3.2.8.2.5D Packaging that involves Si as electronic interconnect
3.2.9.Through-Si-Via (TSV) process flow
3.2.10.Dual Damascene process flow (for inorganic RDL fabrication)
3.2.11.Process flow for Si interposer on package substrate
3.3.Fan out process flows from key companies
3.3.1.SPIL FOEB Technology process flow
3.3.2.ASE FOCoS Process flow (1)
3.3.3.Flip chip on FOWLP - Process flow
3.3.4.Samsung's FOWLP device structure
3.4.Redistribution layer (RDL) & Microvia - Materials
3.4.1.Redistribution Layer (RDL)
3.4.2.Key Factors to Consider When Choosing material for Electronic Interconnects
3.4.3.Dielectric thickness of RDL
3.4.4.Electronic interconnects: SiO2 vs Organic dielectric
3.4.5.Limitations of SiO2 in 2.5D packaging
3.4.6.Electrical characteristics vs different RDL solution - Amkor's perspective
3.4.7.Replace inorganic dielectric with organic polymers?
3.4.8.Importance of low-loss RDL materials for different packaging technologies
3.4.9.Key parameters for organic RDL materials for next generation 2.5D fan-out packaging
3.4.10.Benchmark of organic dielectrics for RDL
3.4.11.Benchmark of material properties used in packaging
3.4.12.Dielectric challenges in fan-out applications - 1
3.4.13.Dielectric challenges in fan-out applications - 2
3.4.14.Industry players of organic RDL
3.4.15.RDL-dielectric suppliers: Toray's polyimide materials
3.4.16.Toray's solution for advanced semiconductor packaging
3.4.17.Low Dk and Low Df materials for RF devices - Solution from Toray
3.4.18.RDL-dielectric suppliers: HD Microsystems
3.4.19.Low-curing temp. RDL from HD Microsystem
3.4.20.RDL-dielectric suppliers: DuPont's Arylalkyl polymers (1)
3.4.21.RDL-dielectric suppliers: DuPont's PID dryfilm
3.4.22.RDL-dielectric suppliers: DuPont's InterVia
3.4.23.RDL-dielectric suppliers: Taiyo Ink's epoxy-based RDL
3.4.24.RDL-dielectric suppliers: Ajinomoto's nanofiller ABF
3.4.25.RDL-dielectric supplier: Showa Denko
3.4.26.Low-loss RDL materials for mmWave: TSMC's InFO AiP
3.4.27.Comparison of polymer dielectric materials in current high performance packages
3.5.Redistribution layer (RDL) & Microvia - Fabrication Processes
3.5.1.Overview of RDL fabrication technology
3.5.2.Semi-Additive Process (SAP) for RDL formation (organic dielectric)
3.5.3.Dual damascene process for RDL formation (organic dielectric)
3.5.4.Benchmark of RDL formation technology
3.5.5.Overview of RDL fabrication technologies
3.5.6.Benchmark of RDL formation technology (cont.)
3.5.7.Overview of RDL L/S range by different RDL formation technology (1)
3.5.8.Overview of microvia creation technology
3.5.9.Fine scale microvia creation technology - technology trend
3.5.10.Overview of via diameter range by different microvia creation technology (1)
3.5.11.Overview of via diameter range by different microvia creation technology (2)
3.5.12.Overview of lithography challenges in high density RDL packaging
3.5.13.Bottlenecks for <2/2 µm L/S RDL Scaling
3.5.14.Two key process considerations for below 2/2 µm L/S organic RDL
3.5.15.Cu dual damascene process for organic RDL formation - TSMC
3.5.16.Embedded Cu trace process - TSMC's high density fan-out package
3.5.17.How RDL affects transmission line loss?
3.5.18.Embedded trace RDL (ETR) process by Amkor (S-SWIFT package)
3.5.19.Embedded trace RDL (ETR) process for RDL formation
3.5.20.Embedded trace RDL (ETR) process for RDL formation
3.5.21.Summary: Organic RDL technology development trend - 1
3.5.22.Summary: Organic RDL technology development trend - 2
3.6.Temporary bonding and debonding
3.6.1.Mitsui Mining and Smelting Co. Ltd. Solution (1)
3.6.2.Mitsui Mining and Smelting Co. Ltd. Solution (2)
3.6.3.Mitsui Mining and Smelting Co. Ltd. Solution (3)
3.7.Epoxy molded compounds (EMC) and mold under fill (MUF)
3.7.1.What are EMC and MUFs?
3.7.2.Epoxy Molding Compound (EMC)
3.7.3.Key parameters for EMC materials
3.7.4.Importance of dielectric constant for EMC used in 5G applications
3.7.5.Experimental and commercial EMC products with low dielectric constant
3.7.6.Epoxy resin: Parameters of different resins and hardener systems
3.7.7.Fillers for EMC
3.7.8.EMC for warpage management
3.7.9.Supply chain for EMC materials
3.7.10.EMC innovation trends for high frequency applications
3.7.11.High warpage control EMC for FO-WLP
3.7.12.Possible solutions for warpage and die shift
3.7.13.EMC suppliers: Sumitomo Bakelite
3.7.14.EMC suppliers: Sumitomo Bakelite
3.7.15.EMC suppliers: Kyocera's EMCs for semiconductors
3.7.16.EMC suppliers: Samsung SDI
3.7.17.EMC suppliers: Showa Denko
3.7.18.EMC suppliers: Showa Denko's sulfur-free EMC
3.7.19.EMC suppliers: KCC Corporation
3.7.20.Molded underfill (MUF)
3.7.21.Liquid molding compound (LMC) for compression molding
4.CU-CU HYBRID BONDING TECHNOLOGY FOR 3D DIE STACKING
4.1.1.Challenges in conventional bumping
4.1.2.Micro bumps (µ bumps) vs bumpless Cu-Cu hybrid bonding
4.1.3.Bonding pitch size needs to scale with TSV development
4.1.4.Performance benchmark of devices based on micro bumps vs Cu-Cu bumpless hybrid bonding - 1
4.1.5.Commercial products that use bumpless Cu-Cu hybrid bonding
4.1.6.Overview of devices that make use of hybrid bonding
4.2.Cu-Cu hybrid bonding - Manufacturing processes
4.2.1.Three ways of Cu-Cu hybrid bonding
4.2.2.D2W (Die-to-Wafer) process
4.2.3.Cu-Cu hybrid bonding manufacturing process flow
4.2.4.Cu-Cu hybrid bonding - Process parameter
4.3.3D SoIC manufacturing processes deep dive
4.3.1.3D SoIC process flow deep dive - 1
4.3.2.3D SoIC process flow deep dive - 2
4.3.3.3D SoIC process flow deep dive - 3
4.3.4.3D SoIC process flow deep dive - 4
4.3.5.Application examples of 3D SoIC packages
4.3.6.Key Applications of 3D SoIC packages
4.3.7.3D SoIC process - A quick overview
4.3.8.Challenges in Cu-Cu hybrid bonding manufacturing process
4.4.Cu-Cu hybrid bonding - The choice of materials
4.4.1.Choices of dielectric materials for hybrid bonding
4.4.2.Key factors in hybrid bonding that are impacted by the choice of dielectric material
4.4.3.Challenges in using inorganic dielectric materials
4.4.4.Benefits of organic dielectric materials
4.4.5.Challenges of using organic dielectric materials
4.4.6.Inorganic dielectric vs organic dielectric: A quick overview
4.4.7.Technology Benchmark of different dielectric materials for Cu-Cu hybrid bonding
4.4.8.Polymer-based dielectric hybrid bonding
4.5.Cu-Cu hybrid bonding based on organic dielectric - Case studies
4.5.1.HD Microsystem 's polyimide solution for hybrid bonding - 1
4.5.2.HD Microsystem 's polyimide solution for hybrid bonding - 2
4.5.3.Showa Denko Copper/Polyimide hybrid bonding - 1
4.5.4.Showa Denko Copper/Polyimide hybrid bonding - 2
4.5.5.Cu/Polymer hybrid bonding simulation results from IME
4.5.6.Polyimide/Cu hybrid bonding materials characterization from Applied Materials & IME
4.5.7.Brewer Science - Photosensitive permanent bonding materials for polymer/Cu hybrid bonding - 1
4.5.8.Brewer Science - Photosensitive permanent bonding materials for polymer/Cu hybrid bonding - 2
4.5.9.Key summary of polymer dielectric for hybrid bonding research
4.5.10.Comparison of polymer case studies for hybrid bonding benchmarking
4.5.11.Benchmark of polymer used for hybrid bonding
4.5.12.Keys to select the right polymer for Cu-Cu hybrid bonding
4.5.13.List of inorganic fillers for CTE improvement in polymers
4.5.14.List of inorganic fillers for thermal conductivity improvement in polymers
4.6.Cu-Cu hybrid bonding based on inorganic dielectric
4.6.1.Samsung's Cu-Cu bonding
4.6.2.Cu-Cu hybrid bonding - Mitsubishi Heavy Industries Machine Tool
4.6.3.Improved Cu-Cu hybrid bonding through Cu enlargement - A study from Tohoku/T-Micro/JCU
4.6.4.1 µm pitch Cu-Cu hybrid bonding base on SiCN - A study from imec
4.6.5.Self-Assembly for Hybrid Bonding - A study from CEA-Leti and Intel
4.6.6.SiO2 C2W Hybrid Bonding from IME
4.6.7.Die stacking from Xperi (Adeia)
4.6.8.XPERI(ADEIA) License map
4.6.9.TSMC hybrid bonding technology for AMD CPU
4.6.10.Stacking DRAMs using hybrid bonding - A study from SK Hynix
4.6.11.Sony's hybrid bonding - Recent development
4.6.12.Key process know-how for inorganic dielectric Cu-Cu hybrid bonding
4.6.13.Cu/Sn-Cu/Sn hybrid bonding
5.MARKET FORECAST
5.1.Forecast: Organic Dielectric Advanced Semiconductor Packaging Module Area (Unit and mm2)
5.2.Forecast: Organic Dielectric Advanced Semiconductor Packaging Module (Unit)
5.3.Forecast: Organic Dielectric Advanced Semiconductor Packaging Module Area (mm2)
5.4.Company profiles
 

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先端半導体パッケージングはorganic dielectric材料に多大な市場機会をもたらします

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