첨단 반도체 패키징 재료 및 공정 기술동향, 주요 업체 및 시장 전망 2025-2035

2.5D, 3D, RDL, 유전체 재료, Cu-Cu 하이브리드 본딩, EMC, MUF, 인터포저, 유리, 공정, FOWLP, FOPLP, 다이 적층, 유기물, 무기물 등 첨단 반도체 패키징 관련 소재 및 공정을 포괄하는 보고서

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이 보고서는 첨단 반도체 패키징에 대한 IDTechEx의 광범위한 지식과 경험을 바탕으로 2.5D 패키징 공정 흐름과 3D 패키징을 위한 혁신적인 Cu-Cu 하이브리드 본딩 기술 등 중요한 기술 동향 및 첨단 반도체 패키징에 사용되는 재료 및 공정 기술에 대한 통찰을 포함하여 유기 유전체 첨단 반도체 패키징 재료 및 공정에 대한 향후 10년간 시장 예측과 전망을 제공합니다.
IDTechEx의 이 보고서는 첨단 반도체 패키징에 사용되는 재료와 공정 기술과 관련하여 다음과 같은 주요 정보를 제공합니다.
 
재료 및 공정 기술 동향
  • 첨단 반도체 패키징 분야 개요 및 핵심 기술 분서
  • 첨단 반도체 패키징 성능 평가의 중요성
  • 제조 공정과 재료가 패키징의 전반적인 효율성에 직접적인 영향을 미치는 방법
  • 제조 공정 흐름, 기술 벤치마크, 업체 평가 및 향후 기술 동향에 대한 종합적인 분석
  • 3D 다이 적층을 위한 선구적인 Cu-Cu 하이브리드 본딩 기술
  • 유기 및 무기 유전체를 모두 사용한 Cu-Cu 하이브리드 본딩의 성공적인 사례 연구
 
시장 전망
  • 유기 유전체 첨단 반도체 패키징 모듈에 대한 10년 시장 예측
  • 향후 10년간 예상되는 시장 성장과 트렌드
 
이 보고서에서 다루는 주요 내용/목차는 아래와 같습니다.
 
1. 첨단 반도체 패키징 개요
 
2. 첨단 반도체 패키징: 성능 평가 및 제조 공정 및 재료와의 연계성
  • 2.5D 패키징 공정 흐름 노하우
  • 재분배층(RDL) 및 마이크로비아 - 재료
  • 재분배층(RDL) 및 마이크로비아 - 제조 공정
  • 에폭시 몰드 컴파운드(EMC) 및 몰드 언더필(MUF)
 
3. 3D 다이 스태킹을 위한 Cu-Cu 하이브리드 본딩 기술
  • Cu-Cu 하이브리드 본딩 - 제조 공정 및 본딩 툴
  • Cu-Cu 하이브리드 본딩 - HBM 스태킹
  • Cu-Cu 하이브리드 본딩 - 재료 선택
  • 유기 유전체에 기반한 Cu-Cu 하이브리드 본딩 - 사례 연구
  • 무기 유전체 기반 Cu-Cu 하이브리드 본딩 - 사례 연구
 
4. 시장 전망
 
As semiconductor packaging technologies evolve, advanced methods like 2.5D and 3D Cu-to-Cu hybrid bonding are essential for achieving higher performance and power efficiency. However, manufacturing these technologies to meet high performance and yield standards while fulfilling client requirements is a complex task. Challenges include developing the right materials and innovating packaging manufacturing techniques. IDTechEx's report,"Materials and Processing for Advanced Semiconductor Packaging 2025-2035: Technologies, Players, Forecasts," offers in-depth insights into these challenges. Drawing on IDTechEx's expertise, the report explores key trends in 2.5D packaging materials and process flow, as well as the innovative Cu-to-Cu hybrid bonding technology for 3D packaging. Additionally, it provides a 10-year market forecast for Organic Dielectric Advanced Semiconductor Packaging Modules, covering unit and area projections, offering valuable foresight for industry stakeholders.
 
 
Source: Materials and Processing for Advanced Semiconductor Packaging 2025-2035: Technologies, Players, Forecasts
2.5D interposer materials:
In 2.5D packaging, different chiplets are interconnected horizontally through interposers, with three main materials being considered: silicon (Si), organic, and glass. Silicon interposers are the industry standard for high-performance computing (HPC) due to their ability to support fine routing, but their high cost and packaging area limitations are challenges. To mitigate these, localized Si bridges are emerging as a solution. Organic interposers offer a cost-effective alternative, particularly through Fan-Out Panel Level Packaging (FOPLP), which increases area utilization and lowers costs by up to 60%. However, achieving fine routing similar to silicon remains difficult. Glass interposers, with their tunable coefficient of thermal expansion (CTE) and high dimensional stability, also support panel-level packaging and cost reduction. Yet, despite their promise, glass interposer production is still maturing, limiting large-scale adoption. As the ecosystem evolves, each material brings its own strengths and challenges to 2.5D packaging, with a focus on balancing performance and cost.
 
 
Benchmark of materials for interposer. (some redaction - full details in purchased report). Source: Materials and Processing for Advanced Semiconductor Packaging 2025-2035: Technologies, Players, Forecasts
Generally, when selecting next-generation materials for interposers in 2.5D semiconductor packaging, five key criteria are essential: dielectric constant (Dk), elongation to failure, coefficient of thermal expansion (CTE), Young's modulus, and moisture absorption. A low Dk is crucial to reduce capacitance and enable higher data rates, improving signal integrity. Elongation to failure ensures the material withstands mechanical stress during manufacturing. Matching the CTE of the dielectric to copper layers enhances package reliability. On the other hand, Young's modulus is also a key factor. While a low Young's modulus minimizes stress on microvias, which is crucial for advanced designs with sub-5 µm vias, a higher modulus offers better stability for the package. Therefore, finding the right balance between these opposing requirements is essential for advanced packaging. Finally, low moisture absorption is critical for long-term reliability, as excessive moisture can lead to delamination and degrade both mechanical and electrical performance. Balancing these parameters is vital for optimizing bandwidth and power efficiency in next-generation interposer materials.
 
Cu-Cu hybrid bonding manufacturing:
Wafer-to-Wafer (W2W) and Die-to-Wafer (D2W) hybrid bonding are two key approaches for 3D hybrid bonding, each with distinct advantages and challenges. W2W bonding, the more established process, involves bonding two full wafers, typically in a single, uniform step. This approach benefits from consistent surface area, making alignment and bonding relatively straightforward. With wafers always maintaining a round shape, the process can be optimized for high throughput, making it suitable for large-scale production. However, W2W bonding is less flexible in handling different chip sizes and is limited by the need to bond identical wafers.
 
On the other hand, D2W hybrid bonding is more complex and addresses the limitations of W2W when dealing with high-performance dies of different sizes. Instead of bonding entire wafers, D2W involves the precise bonding of individual dies onto a target wafer, enabling the integration of different die sizes and types in a single package. This flexibility makes D2W bonding ideal for advanced packaging techniques like chiplet integration, allowing manufacturers to mix and match dies with different functions. However, D2W presents significant manufacturing challenges. D2W demands ultra-clean, particle-free surfaces and precise alignment, as any contamination or misalignment can lead to defects, significantly compromising bonding qualities.
 
Additionally, D2W bonding introduces complications with die aspect ratios. Dies with higher aspect ratios can cause unilateral bonding issues, where the bond front starts along one side, potentially leading to a scaling effect. The use of flexible organic carriers or adhesives during dicing further complicates the process. Moreover, D2W bonding is more sensitive to queue times, which can degrade surface quality before bonding occurs.
 
Despite these challenges, D2W bonding's flexibility and precision are increasingly critical for high-performance applications, while integrated hybrid bonding tools are emerging to address many of these hurdles.
 
 
Three ways of Cu-Cu hybrid bonding. Source: Materials and Processing for Advanced Semiconductor Packaging 2025-2035: Technologies, Players, Forecasts
 
What's covered in this report?
IDTechEx's " Materials and Processing for Advanced Semiconductor Packaging 2025-2035: Technologies, Players, Forecasts" report is divided into four main parts, offering a structured approach to understanding advanced semiconductor packaging. The first part provides a comprehensive introduction to the technologies, development trends, key applications, and ecosystem of advanced semiconductor packaging, providing readers with a solid overview knowledge. The second part focuses on 2.5D packaging processes, delving into crucial aspects including dielectric materials for RDL and Microvia, RDL fabrication techniques, and material selection for EMC and MUF. Each sub-section within this part presents a detailed analysis of process flows, technology benchmarks, player evaluations, and future trends, providing readers with comprehensive insights.
 
The report continues beyond the discussion of 2.5D packaging to the third part, which focuses on the innovative Cu-Cu hybrid bonding technology for 3D die stacking. This section provides valuable insights into the manufacturing process and offers guidance on material selection for optimal outcomes. It also showcases case studies highlighting the successful implementation of Cu-Cu hybrid bonding using both organic and inorganic dielectrics. Additionally, the report includes a 10-year market forecast for the Organic Dielectric Advanced Semiconductor Packaging Module, presented in the last chapter. This forecast encompasses unit and area metrics, providing industry with meaningful perspectives into anticipated market growth and trends for the next decade.
 
Key Aspects
This report provides valuable insights into the materials and processing techniques used in advanced semiconductor packaging, catering to industry professionals seeking informed perspectives on the subject.
 
 
Technology Trends on Materials and Processing
The report begins by introducing readers to the rapidly growing field of advanced semiconductor packaging, laying a solid foundation for the subsequent chapters. These chapters delve into the crucial technologies of advanced semiconductor packaging in detail.
 
The next chapter emphasizes the importance of performance evaluation in advanced semiconductor packaging. It explores how fabrication processes and materials directly impact the overall effectiveness of the packaging. This chapter specifically examines the 2.5D packaging process flow, focusing on essential materials and technologies, including dielectric materials (both inorganic like Si and Glass, and organic materials) for Redistribution Layer (RDL) and Microvia, RDL fabrication techniques, and the choices of materials for Epoxy Molded Compounds (EMC) and Mold Under Fill (MUF). Each sub-section within this chapter provides a comprehensive analysis of fabrication process flows, technology benchmarks, player evaluations, and future technology trends.
 
Transitioning from 2.5D packaging, the subsequent chapter focuses on the pioneering Cu-Cu hybrid bonding technology for 3D die stacking. This section offers valuable insights into the manufacturing process and bonding equipment for Cu-Cu hybrid bonding, providing guidance on material selection for optimal outcomes. Additionally, the chapter presents engaging case studies showcasing the successful implementation of Cu-Cu hybrid bonding using both organic and inorganic dielectrics.
 
 
Market Forecast
The report includes a 10-year market forecast for the Organic Dielectric Advanced Semiconductor Packaging Module, presenting projections for both unit and area metrics. It offers insights into the anticipated market growth and trends over the next decade.
 
This comprehensive report is an essential resource for industry professionals looking to stay informed about the latest advancements and trends in advanced semiconductor packaging.
Report MetricsDetails
Historic Data2022 - 2023
Forecast Period2024 - 2035
Forecast UnitsVolume (units); mm2
Regions CoveredWorldwide
Segments CoveredOrganic Dielectric Advanced Semiconductor Packaging Module Area (Unit and mm2)
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1.EXECUTIVE SUMMARY
1.1.Report scope
1.2.From 1D to 3D semiconductor packaging
1.3.Semiconductor packaging - an overview of technology
1.4.Why advanced semiconductor packaging now?
1.5.Overview of interconnection technique in semiconductor packaging
1.6.2.5D packaging - high density fan-out packaging
1.7.Differences Between FOPLP and FOWLP - 1
1.8.Differences Between FOPLP and FOWLP - 2
1.9.Overview of challenges for FOPLP
1.10.Key trends in fan-out packaging
1.11.Key Factors to Consider When Choosing material for Electronic Interconnects
1.12.Key parameters for organic RDL materials for next generation 2.5D fan-out packaging
1.13.Benchmark of organic dielectrics for RDL
1.14.Industry players of organic RDL
1.15.Comparison of polymer dielectric materials in current high-performance packages
1.16.Benchmark of materials for interposer
1.17.Interposer material supplier landscape
1.18.Benchmark of RDL formation technology
1.19.Overview of RDL L/S range by different RDL formation technology (1)
1.20.Overview of via diameter range by different microvia creation technology (1)
1.21.Overview of via diameter range by different microvia creation technology (2)
1.22.Overview of lithography challenges in high density RDL packaging
1.23.Key parameters for EMC materials
1.24.Evolution of bumping technologies
1.25.Micro bumps (µ bumps) vs bumpless Cu-Cu hybrid bonding
1.26.Overview of devices that make use of hybrid bonding
1.27.Three ways of Cu-Cu hybrid bonding
1.28.Overview of manufacturing factors impacting 3D hybrid bonding quality
1.29.Benchmark: W2W vs Direct D2W
1.30.Benchmark: W2W vs Direct D2W _ Continue
1.31.Benchmark: Collective D2W or Direct D2W
1.32.Overview of surface preparation steps for D2W bonding
1.33.Growing demand for low annealing temperature for 3D hybrid bonding
1.34.Hybrid bonding process options - available performance of current bonding tool
1.35.Integrated hybrid bonding tool
1.36.Key factors in hybrid bonding that are impacted by the choice of dielectric material
1.37.Inorganic dielectric vs organic dielectric: a quick overview
1.38.Technology Benchmark of different dielectric materials for Cu-Cu hybrid bonding
1.39.Key process know-how for inorganic dielectric Cu-Cu hybrid bonding
1.40.Comparison of polymer case studies for hybrid bonding benchmarking
1.41.Key summary of polymer dielectric for hybrid bonding research
1.42.Forecast: Organic Dielectric Advanced Semiconductor Packaging Module Area (Unit and mm2)
2.INTRODUCTION OF ADVANCED SEMICONDUCTOR PACKAGING
2.1.Advanced semiconductor packaging - an overview
2.2.The rise of advanced semiconductor packaging and its challenges
2.3.From 1D to 3D semiconductor packaging
2.4.Semiconductor packaging - an overview of technology
2.5.Overview of interconnection technique in advanced semiconductor packaging
2.6.Fan out wafer level packaging
2.7.Interposer technology
2.8.Interposer structure
2.9.Passive vs Active Interposer
2.10.Interposer alternative - Bridge
2.11.2.5D and 3D IC Packaging
2.12.2.5D IC Packaging
2.13.2.5D IC Packaging
2.14.3D IC Packaging technology
2.15.3D IC Packaging
2.16.3D IC Packaging
2.17.Advanced semiconductor packaging technologies - our scope
2.18.Packaging trend for key markets
2.19.Advanced Semiconductor Packaging - Ecosystem
2.20.Business value chain in the IC industry
2.21.Ecosystem/Business model in the IC industry
2.22.Role and advantages of players in advanced semiconductor packaging market
2.23.Players in advanced semiconductor packaging and their solutions
2.24.An overview of chip supply chain
3.ADVANCED SEMICONDUCTOR PACKAGING: PERFORMANCE EVALUATION AND ITS LINK TO FABRICATION PROCESSES AND MATERIALS
3.1.Introduction
3.1.1.Key factors impacting advanced semiconductor packaging performance
3.1.2.Primary considerations for advanced packaging
3.1.3.The key metrics that impact advanced semiconductor packaging performance: Bandwidth
3.1.4.The definition of IO density
3.1.5.IO density calculation
3.1.6.Routes to increase I/O density
3.1.7.The key metrics that impact advanced semiconductor packaging performance: Power efficiency
3.2.2.5D Packaging Process Flow Know-How
3.2.1.2.5D packaging - high density fan-out packaging
3.2.2.Two types of fan-out: Wafer level
3.2.3.Two types of fan-out: Panel level
3.2.4.Fan-out packaging process overview
3.2.5.Fan-out Chip-first process flow
3.2.6.Fan-out Chip-last process flow
3.2.7.High level process concepts on panel
3.2.8.FOPLP Process Approaches
3.2.9.Key technical challenges for FOPLP
3.2.10.Overview of challenges for FOPLP
3.2.11.Differences Between FOPLP and FOWLP - 1
3.2.12.Differences Between FOPLP and FOWLP - 2
3.2.13.Key trends in fan-out packaging
3.2.14.Wafer level Fan-out chip last RDL formation - development trend
3.2.15.Challenges in future fan-out process
3.2.16.2.5D Packaging that involves Si as electronic interconnect
3.2.17.Through-Si-Via (TSV) process flow
3.2.18.Dual Damascene process flow (for inorganic RDL fabrication)
3.2.19.Process flow for Si interposer on package substrate
3.2.20.Glass core as interposer for advanced semiconductor packaging
3.2.21.Glass core (interposer) package - process flow
3.2.22.Fan out process flows from key companies
3.2.23.TSMC INFO technology - process flow
3.2.24.SPIL FOEB Technology process flow
3.2.25.ASE FOCoS process flow (1)
3.2.26.Flip Chip on FOWLP - Process flow
3.2.27.Samsung's FOWLP device structure
3.3.Redistribution Layer (RDL) & Microvia - Materials
3.3.1.Redistribution Layer (RDL)
3.3.2.Key Factors to Consider When Choosing material for Electronic Interconnects
3.3.3.Dielectric thickness of RDL
3.3.4.Electronic interconnects: SiO2 vs Organic dielectric
3.3.5.Limitations of SiO2 in 2.5D Packaging
3.3.6.Electrical characteristics vs different RDL solution - Amkor's perspective
3.3.7.Replace inorganic dielectric with organic polymers?
3.3.8.Importance of low-loss RDL materials for different packaging technologies
3.3.9.Key parameters for organic RDL materials for next generation 2.5D fan-out packaging
3.3.10.Benchmark of organic dielectrics for RDL
3.3.11.Benchmark of material properties used in packaging
3.3.12.Dielectric challenges in fan-out applications - 1
3.3.13.Dielectric challenges in fan-out applications - 2
3.3.14.Industry players of organic RDL
3.3.15.RDL-dielectric suppliers: Toray's polyimide materials
3.3.16.Toray's solution for advanced semiconductor packaging
3.3.17.Low Dk and Low Df materials for RF devices - solution from Toray
3.3.18.RDL-dielectric suppliers: HD Microsystems
3.3.19.Low-curing temp. RDL from HD Microsystem
3.3.20.RDL-dielectric suppliers: DuPont's Arylalkyl polymers (1)
3.3.21.RDL-dielectric suppliers: DuPont's PID dryfilm
3.3.22.RDL-dielectric suppliers: DuPont's InterVia
3.3.23.RDL-dielectric suppliers: Taiyo Ink's epoxy-based RDL
3.3.24.RDL-dielectric suppliers: Ajinomoto's nanofiller ABF
3.3.25.RDL-dielectric supplier: Showa Denko
3.3.26.Low-loss RDL materials for mmWave: TSMC's InFO AiP
3.3.27.Comparison of polymer dielectric materials in current high-performance packages
3.3.28.Overcoming Limitations of Si interposers with Glass
3.3.29.Glass vs molding compound
3.3.30.TGV - Player and products benchmark
3.3.31.Achieving 2/2 um L/S on glass substrate
3.3.32.Eight metal layer RDL on glass process flow
3.3.33.< 3 um micro via
3.3.34.Challenges of glass packaging
3.3.35.Benchmark of materials for interposer
3.3.36.Interposer material supplier landscape
3.4.Redistribution Layer (RDL) & Microvia - Fabrication Processes
3.4.1.Overview of RDL fabrication technology
3.4.2.Semi-Additive Process (SAP) for RDL formation (organic dielectric)
3.4.3.Dual damascene process for RDL formation (organic dielectric)
3.4.4.Benchmark of RDL formation technology
3.4.5.Benchmark of RDL formation technology (cont.)
3.4.6.Overview of RDL L/S range by different RDL formation technology (1)
3.4.7.Overview of microvia creation technology
3.4.8.Fine scale microvia creation technology - technology trend
3.4.9.Overview of via diameter range by different microvia creation technology (1)
3.4.10.Overview of via diameter range by different microvia creation technology (2)
3.4.11.Overview of lithography challenges in high density RDL packaging
3.4.12.Bottlenecks for < 2/2 µm L/S RDL Scaling
3.4.13.Two key process considerations for below 2/2 µm L/S organic RDL
3.4.14.Cu dual damascene process for organic RDL formation - TSMC
3.4.15.Embedded Cu trace process - TSMC's high density fan-out package
3.4.16.How RDL affects transmission line loss?
3.4.17.Embedded trace RDL (ETR) process by Amkor (S-SWIFT package)
3.4.18.Embedded trace RDL (ETR) process for RDL formation - 1
3.4.19.Embedded trace RDL (ETR) process for RDL formation - 2
3.4.20.Summary: Organic RDL technology development trend - 1
3.4.21.Summary: Organic RDL technology development trend - 2
3.4.22.Temporary bonding and debonding
3.4.23.Mitsui Mining and Smelting Co. Ltd. Solution (1)
3.4.24.Mitsui Mining and Smelting Co. Ltd. Solution (2)
3.4.25.Mitsui Mining and Smelting Co. Ltd. Solution (3)
3.5.Epoxy Molded Compounds (EMC) and Mold Under Fill (MUF)
3.5.1.What are EMC and MUFs?
3.5.2.Epoxy Molding Compound (EMC)
3.5.3.Key parameters for EMC materials
3.5.4.Importance of dielectric constant for EMC used in 5G applications
3.5.5.Experimental and commercial EMC products with low dielectric constant
3.5.6.Epoxy resin: Parameters of different resins and hardener systems
3.5.7.Fillers for EMC
3.5.8.EMC for warpage management
3.5.9.Supply chain for EMC materials
3.5.10.EMC innovation trends for high frequency applications
3.5.11.High warpage control EMC for FO-WLP
3.5.12.Possible solutions for warpage and die shift
3.5.13.EMC suppliers: Sumitomo Bakelite
3.5.14.EMC suppliers: Sumitomo Bakelite
3.5.15.EMC suppliers: Kyocera's EMCs for semiconductors
3.5.16.EMC suppliers: Samsung SDI
3.5.17.EMC suppliers: Showa Denko
3.5.18.EMC suppliers: Showa Denko's sulfur-free EMC
3.5.19.EMC suppliers: KCC Corporation
3.5.20.Molded underfill (MUF)
3.5.21.Liquid molding compound (LMC) for compression molding
4.CU-CU HYBRID BONDING TECHNOLOGY FOR 3D DIE STACKING
4.1.Introduction
4.1.1.Evolution of bumping technologies
4.1.2.Challenges in conventional bumping
4.1.3.Micro bumps (µ bumps) vs bumpless Cu-Cu hybrid bonding
4.1.4.Bonding pitch size needs to scale with TSV development
4.1.5.Performance benchmark of devices based on micro bumps vs Cu-Cu bumpless hybrid bonding - 1
4.1.6.Performance benchmark of devices based on micro bumps vs Cu-Cu bumpless hybrid bonding -2
4.1.7.Commercial products that use bumpless Cu-Cu hybrid bonding
4.1.8.Overview of devices that make use of hybrid bonding
4.1.9.Key concepts about hybrid bonding
4.2.Cu-Cu Hybrid Bonding - Manufacturing Processes and Bonding Tools
4.2.1.Cu-Cu hybrid bonding processes breakdown
4.2.2.Overview of manufacturing factors impacting hybrid bonding quality
4.2.3.Three ways of Cu-Cu hybrid bonding
4.2.4.Generic W2W Process flow
4.2.5.Generic D2W Process flow
4.2.6.W2W hybrid bonding - process parameter
4.2.7.Generic Collective D2W Process
4.2.8.Overview of process comparison Direct D2W Vs W2W Vs. Collective D2W
4.2.9.Benchmark: W2W vs Direct D2W
4.2.10.Benchmark: W2W vs Direct D2W Continued
4.2.11.Benchmark: Collective D2W or Direct D2W
4.2.12.Overview of surface preparation steps for D2W bonding
4.2.13.D2W know-how: Surface treatment
4.2.14.D2W know-how: Contamination management
4.2.15.D2W know-how: Die placement and tool consideration
4.2.16.Annealing temperature for hybrid bonding
4.2.17.Growing demand for low annealing temperature
4.2.18.Approaches to lower annealing temperature
4.2.19.Room temperature hybrid bonding - CEA-Leti
4.2.20.Hybrid bonding tool development
4.2.21.Hybrid bonding process options - available performance of current bonding tool
4.2.22.State-of-the-art D2W bonder from Besi
4.2.23.Besi's portfolio on multiple 3D technologies
4.2.24.State-of-the-art W2W and D2E bonder from EVG
4.2.25.Applied Materials Portfolio in Advanced Semiconductor Packaging
4.2.26.Integrated hybrid bonding tool
4.2.27.Integrated D2W Hybrid bonding process flow
4.2.28.3D SoIC manufacturing processes deep dive
4.2.29.3D SoIC process flow deep dive - 1
4.2.30.3D SoIC process flow deep dive - 2
4.2.31.3D SoIC process flow deep dive - 3
4.2.32.3D SoIC process flow deep dive - 4
4.2.33.Application examples of 3D SoIC packages
4.2.34.3D SoIC process - a quick overview
4.2.35.Challenges in Cu-Cu hybrid bonding manufacturing process
4.3.HBM Stacking Using 3D Hybrid Bonding
4.3.1.HBM generations - specification benchmark
4.3.2.Key highlights regarding HBM development from Semicon Taiwan 2024
4.3.3.HBM packaging challenges - bonding technologies
4.3.4.HBM Packaging: TC-NCF vs MR-MUF
4.3.5.MR-MUF for next generation HBM before transitioning to hybrid bonding - 1
4.3.6.MR-MUF for next generation HBM before transitioning to hybrid bonding - 2
4.3.7.MR-MUF for next generation HBM before transitioning to hybrid bonding - 3
4.3.8.HBM packaging - limitations of micro-bump
4.3.9.C2W bonding for next generation HBM - SK Hynix
4.3.10.Hybrid bonding for HBM packaging - Samsung's findings and roadmap
4.3.11.Hybrid bonding for HBM packaging - Samsung's findings and roadmap continue
4.3.12.Process Flow for Memory Stacking Using D2W Hybrid Bonding - 1
4.3.13.Process Flow for Memory Stacking Using D2W Hybrid Bonding - 2
4.4.Cu-Cu Hybrid Bonding - The Choice of Materials
4.4.1.Choices of dielectric materials for hybrid bonding
4.4.2.Key factors in hybrid bonding that are impacted by the choice of dielectric material
4.4.3.Challenges in using inorganic dielectric materials
4.4.4.Benefits of organic dielectric materials
4.4.5.Challenges of using organic dielectric materials
4.4.6.Inorganic dielectric vs organic dielectric: a quick overview
4.4.7.Technology Benchmark of different dielectric materials for Cu-Cu hybrid bonding
4.4.8.Polymer-based dielectric hybrid bonding
4.5.Cu-Cu Hybrid Bonding Based on Organic Dielectric - Case Studies
4.5.1.HD Microsystem 's polyimide solution for hybrid bonding - 1
4.5.2.HD Microsystem 's polyimide solution for hybrid bonding - 2
4.5.3.Showa Denko Copper/Polyimide hybrid bonding - 1
4.5.4.Showa Denko Copper/Polyimide hybrid bonding - 2
4.5.5.Cu/Polymer hybrid bonding simulation results from IME
4.5.6.Polyimide/Cu hybrid bonding materials characterization from Applied Materials & IME
4.5.7.Brewer Science - photosensitive permanent bonding materials for polymer/Cu hybrid bonding - 1
4.5.8.Brewer Science - photosensitive permanent bonding materials for polymer/Cu hybrid bonding - 2
4.5.9.Key summary of polymer dielectric for hybrid bonding research
4.5.10.Comparison of polymer case studies for hybrid bonding benchmarking.
4.5.11.Keys to select the right polymer for Cu-Cu hybrid bonding
4.5.12.List of inorganic fillers for CTE improvement in polymers
4.5.13.List of inorganic fillers for thermal conductivity improvement in polymers
4.6.Cu-Cu Hybrid Bonding Based on Inorganic Dielectric
4.6.1.Samsung's Cu-Cu bonding
4.6.2.Cu-Cu hybrid bonding - Mitsubishi Heavy Industries Machine Tool
4.6.3.Improved Cu-Cu hybrid bonding through Cu enlargement - a study from Tohoku/T-Micro/JCU
4.6.4.1 µm pitch Cu-Cu hybrid bonding base on SiCN - a study from imec
4.6.5.Self-Assembly for Hybrid Bonding - A study from CEA-Leti and Intel
4.6.6.SiO2 C2W Hybrid Bonding from IME
4.6.7.Die stacking from Xperi (Adeia)
4.6.8.XPERI(ADEIA) License map
4.6.9.TSMC hybrid bonding technology for AMD CPU
4.6.10.Stacking DRAMs using hybrid bonding - a study from SK Hynix
4.6.11.Sony's hybrid bonding - recent development
4.6.12.Key process know-how for inorganic dielectric Cu-Cu hybrid bonding
4.6.13.Cu/Sn-Cu/Sn hybrid bonding
5.MARKET FORECAST
5.1.Forecast: Organic Dielectric Advanced Semiconductor Packaging Module Area (Unit and mm2)
5.2.Forecast: Organic Dielectric Advanced Semiconductor Packaging Module (Unit)
5.3.Forecast: Organic Dielectric Advanced Semiconductor Packaging Module Area (mm2)
 

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