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Co-Packaged Optics (CPO) 2025-2035: Technologies, Market, and Forecasts

CPO, optical interconnects, optical IO, data center, switches, AI, advanced semiconductor packaging, 2.5D, 3D, optical engine, EIC, PIC

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The rise of Co-Packaged Optics (CPO)
Over the past decade, the capacity of data center Ethernet switches has surged from 0.64 Tbps to 25.6 Tbps, driven by the adoption of 64x 400 Gbps or 32x 800 Gbps pluggable optical transceiver modules. However, these high-speed modules, within their current form factors, pose significant challenges. Issues include the required densities of electrical and optical connectors, as well as escalating power consumption.
 
To achieve next-generation optical engines supporting 800 Gbps and beyond per module, the communication rate must double to at least 100 Gbps per lane. This increase introduces substantial signal integrity issues across the switch socket, motherboard, and edge connector, leading to heightened power dissipation at SerDes interfaces. In future Ethernet switching, these signal integrity problems may cause I/O power consumption to exceed that of the switch core. Additionally, the integration density of standard pluggable modules is limited by the QSFP/OSFP form factor, necessitating advanced thermal management solutions not yet widely available.
 
Co-Packaged Optics (CPO) presents a promising solution to these challenges. Unlike traditional pluggable models, CPO integrates optical modules directly onto the switch ASIC substrate, reducing electrical reach and effectively addressing signal integrity issues. This approach has gained traction among major data centers. However, optimizing the packaging strategy for CPO remains a topic of ongoing industry discussion and development. IDTechEx's latest report, "Co-Packaged Optics 2025-2035: Technologies, Market, and Forecasts," explores these advancements in CPO technology and packaging techniques enabling its adoption.
 
 
Key trend of optical transceiver in high-end data center. Source: IDTechEx
The importance of advanced semiconductor packaging technologies for Co-Packaged Optics (CPO)
The integration of CPO in data centers aims to boost I/O bandwidth and reduce energy consumption. The way photonic integrated circuits (PICs) are combined with electronic integrated circuits (EICs) and switch ICs can significantly influence the areal and edge bandwidth density, as well as packaging parasitics. These factors directly affect the transceiver's I/O bandwidth and energy efficiency, meaning improper integration can negate the advantages of silicon photonics.
 
For CPO, the integration of photonic and electronic components can be achieved through various methods, each with unique advantages and challenges. The most advanced and still in the R&D phase is the 3D monolithic integration embeds photonic components within an existing electronic process node with minimal alterations, co-locating active photonics and driving electronics within the same die. This reduces parasitics and simplifies packaging by eliminating the need for interface pads and bumps. However, monolithic integration typically uses older CMOS nodes, resulting in suboptimal photonic performance and higher energy consumption. Despite these limitations, it offers minimal impedance mismatch and simplified packaging.
 
Conversely, 2D integration places the PIC and EIC side by side on a PCB, connected by wire bonds or flip-chip. This method is straightforward and cost-effective, but introduces significant parasitic inductance, limiting aggregate I/O due to single-edge connections. While 2D integration is easy to package, the reliance on wirebonds constrains the transceiver bandwidth and increases energy consumption, making it less efficient for high-performance applications.
 
3D hybrid integration offers a more advanced solution by placing the EIC on top of the PIC, via various advanced semiconductor packaging technologies, including Through-Si-Via (TSV), high density fan-out, Cu-Cu hybrid bonding, active photonic interposer, etc, significantly reducing parasitics. The use of advanced semiconductor packaging technologies in 3D integration allows for dense pitch capabilities, enhancing performance. However, thermal dissipation remains a challenge, as the heat generated by the EIC can impact the PIC, necessitating advanced thermal management solutions. Despite these thermal challenges, 3D hybrid integration achieves higher performance due to minimized packaging parasitics.
 
2.5D integration serves as a compromise, with both the EIC and PIC flip-chipped onto a passive interposer with TSVs. This approach maintains manageable parasitics and dense pitch capabilities similar to 3D integration but adds complexity with the need for interposer traces. While 2.5D integration balances performance, cost, and fabrication turnaround, it incurs higher parasitics than 3D hybrid integration.
 
In summary, each integration method presents trade-offs between performance, complexity, and cost, guiding the choice based on specific application requirements and constraints.
 
Co-Packaged Optics (CPO) Market trajectory
According to IDTechEx, the Co-Packaged Optics (CPO) market is projected to exceed $1.2 billion by 2035, growing at a robust CAGR of 28.9% from 2025 to 2035. CPO network switches are expected to dominate revenue generation, driven by each switch potentially incorporating up to 16 CPO PICs. Optical interconnects for AI system will constitute approximately 20% of the market, with each AI accelerator typically utilizing one optical interconnect PIC to meet increasing demands for high-speed data processing and communication in advanced computing applications.
 
 
Total CPO market growth 2025 vs 2035. Source: IDTechEx
 
IDTechEx's report, titled "Co-Packaged Optics (CPO) 2025-2035: Technologies, Market, and Forecasts," offers an extensive exploration into the latest advancements within co-packaged optics technology. The report delves deep into key technical innovations and packaging trends, providing a comprehensive analysis of the entire value chain. It thoroughly evaluates the activities of major industry players and delivers detailed market forecasts, projecting how the adoption of CPO will reshape the landscape of future data center architecture.
 
Central to the report is the recognition of advanced semiconductor packaging as the cornerstone of co-packaged optics technology. IDTechEx places significant emphasis on understanding the potential roles that various semiconductor packaging technologies may play within the realm of CPO.
 
Key aspects of the report include:
This report provides a comprehensive analysis of Co-Packaged Optics (CPO), encompassing various critical aspects:
  • Market Dynamics: Examination of key players such as Nvidia, Broadcom, Cisco, Ranovus, and Intel, and the forces shaping the CPO landscape.
  • Innovations in CPO Design: Exploration of advanced CPO designs and their implications for enhancing data center efficiency and shaping future architecture.
  • Semiconductor Packaging Breakthroughs: Insight into the latest advancements in semiconductor packaging, including 2.5D and 3D technologies, and their role in enabling CPO innovation.
  • Optical Engines: Analysis of the drivers behind CPO's performance and efficiency advantages.
  • CPO for AI Interconnects: Exploration of how optical I/O can address the limitations of copper connections in AI applications, improving efficiency, latency, and data rates.
  • CPO for Switches: Assessment of the potential 25% efficiency gains in high-performance network switches through CPO integration.
  • Challenges and Solutions: Critical review of obstacles to CPO adoption and strategies to overcome them.
  • Future Analysis: Predictions and insights into the next generation of CPO and its anticipated impact on the industry.
 
The report is based on extensive research and interviews with industry experts and provides valuable insights for anyone interested in gaining a strategic understanding of Co-Packaged Optics' role in advancing the future of data center and AI technology.
  • Market Forecasts-10-year Data Center Population Cumulative Forecast
  • 10-year AI Accelerator Unit Shipments Forecast
  • 10-year CPO Interconnect for AI (Optical I/O) Unit Shipments Forecast
  • 10-year CPO Interconnect for AI (Optical I/O) Market Revenue Forecast
  • 10-year CPO-enabled Network Switch Unit Shipments Forecast
  • 10-year CPO-enabled Network Switch Market Revenue Forecast
  • 10-year Total CPO Market Revenue Forecast
 
 
Report MetricsDetails
Historic DataFrom 2022
CAGRThe total CPO market is set to be worth more than $1.2 billion by 2035, with a CAGR of 28.9%
Forecast Period2024 - 2035
Regions CoveredWorldwide
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Further information
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1.EXECUTIVE SUMMARY
1.1.What does a modern high-performance AI data center look like?
1.2.Switches: Key Components in Modern Data Center
1.3.Advancements in Switch IC Bandwidth and the Need for Co-Packaged Optics (CPO) Technology
1.4.Overview of key challenges in data center architectures
1.5.Key trend of optical transceiver in high-end data center
1.6.Design decisions for CPO compared to Pluggables
1.7.What is Optical Engine (OE)
1.8.Heterogeneous Integration and Co-Packaged Optics (CPO)
1.9.Overview of interconnection technique in semiconductor packaging
1.10.Key CPO applications: network switch and computing optical I/O
1.11.EIC/PIC integration by advanced interconnect technique
1.12.2D to 3D EIC/PIC integration options
1.13.Benchmark table of different packaging technologies for EIC/PIC
1.14.Examples of packaging a 3D optical engine with an IC
1.15.Three types of CPO + XPU/switch ASIC packaging structures
1.16.3.2 Tb/s CPO module defined by the Optical Internetworking Forum (OIF) - 1
1.17.Nvidia's 3D integration of SoC, HBM, EIC and PIC on co-packaged substrates (TSV interposer)
1.18.Benchmark of different laser integration technology
1.19.Challenges and Future Potential of CPO Technology
1.20.CPO Demonstration Products Benchmarked
1.21.Future AI Architecture predicted by IDTechEx
1.22.Optical I/O for AI interconnect CPO Forecast (Units Shipped)
1.23.Optical I/O for AI interconnect CPO Forecast (Revenue/Market Size)
1.24.CPO Network Switches (L2 Switches) for AI accelerators Forecast (Units Shipped)
1.25.CPO Network Switches (L2 Switches) for AI accelerators Forecast (Market Size and Revenue)
1.26.Total CPO Market
1.27.Total CPO unit shipped by different EIC/PIC integration technology (millions)
1.28.System integration of Network Switches (L2 Switches) for AI accelerators Forecast by packaging technologies (Unit shipped)
1.29.System integration of Optical I/O Forecast by packaging technologies (Units Shipped)
2.CHALLENGES AND SOLUTIONS FOR FUTURE AI SYSTEM
2.1.Introduction
2.1.1.The rise and the challenges of LLM
2.1.2.What does a modern high-performance AI data center look like?
2.1.3.Closer look into NVIDIA's state-of-the-art AI system
2.1.4.Switches: Key Components in Modern Data Center
2.2.Challenges in Network Switches interconnect for high-end data centers
2.2.1.Roadmap of interconnect technology for network switches in high-end data center
2.2.2.Serdes bottleneck in high-bandwidth systems
2.2.3.Solutions to Serdes bottlenecks in high-bandwidth systems
2.2.4.Pluggable optics - what are the bottlenecks?
2.2.5.On-Board Optics (OBO)
2.2.6.Co-Packaged Optics (CPO)
2.2.7.Transmission Losses in a Pluggable Optical Transceiver Connection
2.2.8.Pluggable optics vs CPO
2.2.9.Design decisions for CPO compared to Pluggables
2.2.10.Advancements in Switch IC Bandwidth and the Need for CPO Technology
2.2.11.L2 Frontside Network Architecture Diagram CPO versus non-CPO
2.3.Challenges in Compute Switches interconnect (i.e. Optical I/O) for high-end data centers
2.3.1.High performance connections are required for AI
2.3.2.Number of Cu wires in current AI system Interconnects
2.3.3.Limitations in current copper systems in AI
2.3.4.Nvidia's Connectivity Choices: Copper vs. Optical for High-Bandwidth Systems
2.3.5.Copper vs. Optical for High-Bandwidth Systems: Benchmark
2.3.6.Moving from Cu to Optical interconnects for high-end AI system
2.3.7.Current AI system Architecture
2.3.8.L1 Backside Compute Architecture with Cu systems
2.3.9.L1 Backside Compute Architecture with Optical Interconnect: Co-Packaged Optics (CPO)
2.3.10.Opportunities for swapping copper interconnects to optical connects:
2.4.Future AI system in high-end data center
2.4.1.Power efficiency comparison: CPO vs. pluggable optics vs. Copper Interconnects
2.4.2.Latency of 60cm Data Transmission Technology Benchmark
2.4.3.Future AI Architecture predicted by IDTechEx
3.INTRODUCTION TO CO-PACKAGED OPTICS (CPO)
3.1.What's covered in this chapter
3.2.PICs Key Concepts
3.2.1.What are Photonic Integrated Circuits (PICs)?
3.2.2.PICs vs Silicon Photonics - what are the differences
3.2.3.PIC Architecture
3.2.4.Advantages and Challenges of PIC
3.3.Optical Engine (OE)
3.3.1.What is Optical Engine
3.3.2.How an Optical Engine Works
3.3.3.Optical Power Supplies
3.4.Co-packaged Optics
3.4.1.Three key concepts in co-packaged optics (CPO)
3.4.2.Key technology building blocks for CPO
3.4.3.Benefits of CPO: Latency
3.4.4.Benefits of CPO: Power Consumption
3.4.5.Benefits of CPO: Data Rate
3.4.6.Overview of value proposition of CPO
3.4.7.Future challenges in CPO
4.PACKAGING FOR CO-PACKAGED OPTICS (CPO)
4.1.Introduction
4.1.1.Key components to be packaged in an optical transceiver
4.1.2.Heterogeneous Integration and Co-Packaged Photonics
4.1.3.CPO for network switch - packaging concept
4.1.4.Example: 1.6 Tbps Co-packaged optics for network switch
4.1.5.CPO as optical I/O for XPUs - packaging concept
4.1.6.CPO as optical I/O for XPUs - packaging concept (follow)
4.1.7.Example: CPO integration for compute silicon
4.1.8.Overview of CPO packaging technologies
4.2.Overview and development roadmap of 2.5D and 3D Advanced Semiconductor Packaging Technologies
4.2.1.Evolution roadmap of semiconductor packaging
4.2.2.Semiconductor packaging - an overview of technology
4.2.3.Key metrics for advanced semiconductor packaging performance
4.2.4.Overview of interconnection technique in semiconductor packaging
4.2.5.Overview of 2.5D packaging structure
4.2.6.Interconnection technique - Interposer
4.2.7.Passive vs Active Interposer
4.2.8.Interposer Structure: RDL & Through-Si-Via
4.2.9.2.5D advanced semiconductor packaging technology portfolio
4.3.2.5D Si-based Packaging technologies
4.3.1.2.5D packaging that involves Si as interconnect
4.3.2.Through Si Via (TSV) - now and the future
4.3.3.Developing trend for 2.5D Si-based packaging
4.3.4.Si interposer vs Si bridge benchmark
4.4.2.5D Organic-based Packaging technologies
4.4.1.2.5D packaging - high density fan-out (FO) packaging
4.4.2.Redistribution Layer (RDL)
4.4.3.Electronic interconnects: SiO2 vs Organic dielectric
4.4.4.Two types of fan-out: Panel level
4.4.5.Two types of fan-out: Wafer level
4.4.6.Wafer level Fan-out vs Panel level Fan-out : The differences
4.4.7.Key trends in fan-out packaging
4.4.8.Challenges in future fan-out process
4.5.2.5D Glass-based Packaging technologies
4.5.1.Roles of glass in semiconductor packaging
4.5.2.Glass core as interposer for advanced semiconductor packaging
4.5.3.Overcoming Limitations of Si interposers with Glass
4.5.4.Glass vs molding compound
4.5.5.Glass core (interposer) package - process flow
4.5.6.Challenges of glass packaging
4.6.3D Advanced Semiconductor Packaging technologies
4.6.1.Evolution of bumping technologies
4.6.2.Challenges in scaling bumps
4.6.3.µ bump for advanced semiconductor packaging
4.6.4.Bumpless Cu-Cu hybrid bonding
4.6.5.Three ways of Cu-Cu hybrid bonding: benchmark
4.6.6.Challenges in Cu-Cu hybrid bonding manufacturing process
4.7.CPO packaging: EIC and PIC integration
4.7.1.EIC/PIC integration - by conventional interconnect technique
4.7.2.EIC/PIC integration by emerging interconnect technique
4.7.3.2D to 3D EIC/PIC integration options
4.7.4.Benchmark table of different packaging technologies for EIC/PIC
4.7.5.Pros and Cons of 2D integration of EIC/PIC
4.7.6.Pros and Cons of 2.5D integration of EIC/PIC
4.7.7.Pros and Cons of 3D hybrid integration of EIC/PIC
4.7.8.Pros and Cons of 3D monolithic integration of EIC/PIC
4.8.TSV for EIC/PIC integration
4.8.1.TSV for EIC/PIC integration in CPO
4.8.2.Why using TSV for PIC and EIC integration
4.8.3.Cisco packaging architectures of optical engine over generations
4.8.4.Cisco: 2.5D Chip-on-Chip (CoC) Packaging Architecture for EIC/PIC integration
4.8.5.Cisco: 3D TSV for PIC/EIC integration
4.8.6.Key TSV Fabrication Steps and Challenges in CPO - 1
4.8.7.Key TSV Fabrication Steps and Challenges in CPO - 2
4.8.8.Packaging options for silicon photonics - w/ or w/o TSV?
4.8.9.Pros and Cons of 2.5D Si interposer for EIC/PIC integration
4.9.Fan-out for EIC/PIC integration
4.9.1.ASE's proposed fan-out solution for CPO packaging
4.9.2.FOPOP from ASE - process
4.9.3.Detailed analysis of FOPOP vs WB packaging for CPO
4.9.4.Optical Packaging Process Considerations for Silicon Photonics - ASE
4.9.5.SPIL's Fan-Out Embedded Bridge (FOEB) Structure for PIC/EIC integration in CPO
4.9.6.Process flow of integrating PIC and EIC in a FOEB structure
4.9.7.Process challenges in packaging OE
4.9.8.Rockley Photonics proposes FOWLP for CPO packaging structure
4.9.9.Rockley Photonics's FOWLP CPO packaging process flow - 1
4.9.10.Rockley Photonics's FOWLP CPO packaging process flow - 2
4.9.11.Challenges of using fan-out for EIC/PIC integration
4.10.Glass-based CPO Packaging technologies
4.10.1.Glass-based Co-packaged optics - Corning's vision
4.10.2.Glass-based Co-packaged optics - Packaging structure
4.10.3.Glass-based Co-packaged optics - process development
4.10.4.Corning's 102.4 Tb/s test vehicle
4.11.Hybrid bonding for EIC/PIC integration
4.11.1.TSMC's advanced semiconductor packaging technology portfolio
4.11.2.TSMC: Integrated HPC Technology Platform for AI
4.11.3.Optical Engine Roadmap from TSMC - 1
4.11.4.Optical Engine Roadmap from TSMC - 2
4.11.5.iOIS - Integrated Optical Interconnection System from TSMC
4.11.6.Combining EIC and PIC with 3D SoIC bond
4.11.7.TSMC 3D SoIC Technology
4.11.8.Roadmap of bond pitch scaling
4.12.System integration of OE and ASIC/XPU, etc
4.12.1.Co-packaging vs Co-packaged optics (CPO)
4.12.2.Three types of CPO + XPU/switch ASIC packaging structures
4.12.3.Examples of packaging an optical engine with an integrated circuit (IC) in a 2D or 2.5D configuration
4.12.4.OE integration with ASIC in a 2.5D configuration
4.12.5.Examples of packaging an optical engine with an integrated circuit (IC) in a 3D configuration
4.12.6.Future 3D-CPO structure
4.12.7.Nvidia's 3D integration of SoC, HBM, EIC and PIC on co-packaged substrates (TSV interposer)
4.12.8.Example of a 51.2 Tb/s switch module based on 3D integration of EIC/PIC
4.12.9.Process in fabrication of the 3D heterogeneous integration of EIC and PIC on a glass interposer
4.12.10.Example of a switch module based on 3D integration of EIC/PIC on glass interposer
4.12.11.Challenges and Future Potential of CPO Technology
4.13.Optical alignment and Laser integration
4.13.1.Grating vs. Edge Couplers: Challenges in High-Density Optical I/O for Silicon Photonics
4.13.2.Optical alignment challenges and solutions - 1
4.13.3.Optical alignment challenges and solutions - 2
4.13.4.Optical alignment challenges and solutions - 3
4.13.5.Two alignment approaches
4.13.6.Reducing optical fiber packaging complexity
4.13.7.On-chip light source integration methods
4.13.8.External Lasers for CPO (1)
4.13.9.External Lasers for CPO (2)
4.13.10.Laser attach technology benchmark - 1
4.13.11.Laser attach technology benchmark - 2
4.13.12.Benchmark of different laser integration technology
4.13.13.Key technical challenge: the size mismatch between silicon waveguides and planar optical fibers
4.13.14.Case studies: polymer waveguide on a Silicon-photonics-embedded interposer for CPO
4.13.15.Processes overview for Silicon-photonics-embedded interposer for CPO
4.13.16.SHINKO organic substrate with polymer optical waveguides
5.KEW SWITCH COMPANY CPO DESIGN AND ROADMAP
5.1.3.2 Tb/s CPO module defined by the Optical Internetworking Forum (OIF) - 1
5.2.3.2 Tb/s CPO module defined by the Optical Internetworking Forum (OIF) - 1
5.3.CPO Demonstration Products Benchmarked
5.4.Cisco Co-Packaged Optics Demo
5.5.Cisco: CPO Power Efficiency
5.6.Cisco: External Lasers (ELFPP)
5.7.Broadcom
5.8.Broadcom Switch and Nvidia Switch compared
5.9.Broadcom's CPO development timeline
5.10.Broadcom's CPO portfolio
5.11.Intel Optical Compute Interconnect
5.12.Intel Optical Compute Interconnect (2)
5.13.Nvidia: Opportunities for Co-Packaged Optics
5.14.Nvidia: Challenges and Final Thoughts for Co-Packaged Optics
5.15.Ranovus products and progress
5.16.UALink
5.17.Ayer Labs TeraPHY
6.MARKET FORECASTS
6.1.Data Center Forecast Methodology
6.2.Global Data Center Population and AI Accelerator Unit Forecasts
6.3.Optical I/O for AI interconnect CPO Forecast (Units Shipped)
6.4.Optical I/O for AI interconnect CPO Forecast (Revenue/Market Size)
6.5.CPO Network Switches (L2 Switches) for AI accelerators Forecast (Units Shipped)
6.6.CPO Network Switches (L2 Switches) for AI accelerators Data Table (Units Shipped)
6.7.CPO Network Switches (L2 Switches) for AI accelerators Forecast (Market Size and Revenue)
6.8.Total CPO Market
6.9.Total CPO by different EIC/PIC integration technology (unit shipment, millions)
6.10.System integration of Network Switches (L2 Switches) for AI accelerators Forecast by packaging technologies (Unit shipped)
6.11.System integration of Optical I/O Forecast by packaging technologies (Units Shipped)
6.12.Table for CPO unit forecast by packaging technologies
7.COMPANY PROFILES
7.1.ACCRETECH (Grinding Tool)
7.2.AEPONYX
7.3.Amkor — Advanced Semiconductor Packaging
7.4.ASE — Advanced Semiconductor Packaging
7.5.Ayar Labs: AI Accelerator Interconnect
7.6.CEA-Leti (Advanced Semiconductor Packaging)
7.7.Coherent: Photonic Integrated Circuit-Based Transceivers
7.8.EFFECT Photonics
7.9.EVG (3D Hybrid Bonding Tool)
7.10.GlobalFoundries
7.11.HD Microsystems
7.12.Henkel (Semiconductor packaging, Adhesive Technologies division)
7.13.iPronics: Programmable Photonic Integrated Circuits
7.14.JCET Group
7.15.JSR Corporation
7.16.Lightelligence
7.17.Lightmatter
7.18.LioniX
7.19.LIPAC
7.20.LPKF
7.21.Mitsui Mining & Smelting (Advanced Semiconductor Packaging)
7.22.NanoWired
7.23.Resonac (RDL Insulation Layer)
7.24.Scintil Photonics
7.25.TOK
7.26.TSMC (Advanced Semiconductor Packaging)
7.27.Vitron (Through-Glass Via Manufacturing) — A LPKF Trademark
 

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The total CPO market is set to be worth more than US$1.2 billion by 2035, with a CAGR of 28.9%

Report Statistics

Slides 242
Companies 27
Forecasts to 2035
 

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ISBN: 9781835700471

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