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1. | EXECUTIVE SUMMARY & CONCLUSIONS |
1.1. | General electronic packaging - an overview |
1.2. | Advanced semiconductor packaging - an overview |
1.3. | Advanced semiconductor packaging technologies - Our scope |
1.4. | Semiconductor packaging - an overview of technology |
1.5. | From 1D to 3D semiconductor packaging |
1.6. | The rise of advanced semiconductor packaging and its challenges |
1.7. | Four key drivers for advanced semiconductor packaging technologies |
1.8. | Key figures of merit of advanced semiconductor packaging technologies |
1.9. | Packaging trend for key markets |
1.10. | Players in advanced semiconductor packaging and their solutions |
1.11. | Players in advanced semiconductor packaging by geography |
1.12. | HPC chip supply chain analysis |
1.13. | High-end commercial chips based on advanced semiconductor packaging technology (1) |
1.14. | High-end commercial chips based on advanced semiconductor packaging technology (2) |
1.15. | Investment in advanced semiconductor packaging by companies |
1.16. | Semiconductor foundries and their roadmap |
1.17. | Business value chain in IC industry |
1.18. | Ecosystem/Business model in the IC industry |
1.19. | Future packaging trend for chiplet server CPU |
1.20. | Data Center Server Unit Forecast 2022-2033 (Shipment) |
1.21. | Total addressable data center CPU market forecast 2022-2033 (Shipment) |
1.22. | Data center CPU: advanced semiconductor packaging unit forecast 2022-2033 (Shipment) |
1.23. | Future ADAS/Autonomous driving systems: requirements, actions, and current challenges |
1.24. | Three transformational pillars in automotive electronics |
1.25. | L4+ Autonomous vehicles sales forecast 2022-2045 |
1.26. | Total addressable ADAS processor & accelerator sales market for L4+ Autonomous vehicles forecast 2022-2045 |
1.27. | 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045 |
1.28. | 3D advanced semiconductor packaging unit sales for L4+ Autonomous vehicles forecast 2022-2045 |
1.29. | Unit sales forecast for smartphones/tablets/smartwatches/AR/VR/MR 2022-2033 |
1.30. | Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (1) |
1.31. | Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (2) |
1.32. | Global PC shipment forecast 2022-2033 |
1.33. | Advanced semiconductor packaging units in PC forecast 2022-2033 (1) |
1.34. | Advanced semiconductor packaging units in PC forecast 2022-2033 (2) |
1.35. | 5G radios by MIMO size unit forecast 2022-2032 (Cumulative) |
1.36. | Estimating the total addressable market for advanced semiconductor packaging in 5G RAN infrastructure 2022-2032 (Cumulative) |
1.37. | Advanced semiconductor packaging unit for 5G RAN networks 2022-2032 (Cumulative) |
1.38. | Summary |
1.39. | Company profiles |
2. | INTRODUCTION |
2.1. | Si IC: technology trend |
2.2. | Paving the way to the data-centric future |
2.3. | Fundamentals of abundance data computing system |
2.4. | Key parameter of growth for processor and memory (1) |
2.5. | Key parameter of growth for processor and memory (2) |
2.6. | Memory bandwidth deficit |
2.7. | Four key area of growth for abundance data computing system |
2.8. | The economics of scaling |
2.9. | Scaling technology roadmap overview |
2.10. | Transistor device development (1) |
2.11. | Transistor device development (2) |
2.12. | Key parameters for transistor device scaling |
2.13. | Evolution of transistor device architectures |
2.14. | CNTs for transistors |
2.15. | CNFET research breakthrough (1) |
2.16. | CNFET research breakthrough (2) |
2.17. | CNFET case study (1) |
2.18. | 3D SOC |
2.19. | On-chip memory |
2.20. | Routes to increase I/O density |
2.21. | Si IC players analysis - research and manufacturing roadmap |
2.22. | Roadmap of pioneering companies in Si advanced process node |
2.23. | The players in Si advanced process node |
2.24. | TSMC (1) |
2.25. | TSMC (2) |
2.26. | TSMC (3) |
2.27. | TSMC (4) |
2.28. | Intel (1) |
2.29. | Intel (2) |
2.30. | Intel (3) |
2.31. | Samsung (1) |
2.32. | Samsung (2) |
2.33. | Semiconductor foundries and their roadmap |
2.34. | Advanced semiconductor packaging technologies - introduction and technology trend |
2.35. | General electronic packaging - an overview |
2.36. | Advanced semiconductor packaging - an overview |
2.37. | Semiconductor packaging - an overview of technology |
2.38. | From 1D to 3D semiconductor packaging |
2.39. | The rise of advanced semiconductor packaging and its challenges |
2.40. | Four key drivers for advanced semiconductor packaging technologies |
2.41. | Key figures of merit of advanced semiconductor packaging technologies |
2.42. | Packaging trend for key markets |
2.43. | Advanced semiconductor packaging technologies - our scope |
2.44. | Business value chain in IC industry |
2.45. | Ecosystem/Business model in the IC industry |
2.46. | Role and advantages of players in advanced semiconductor packaging market |
2.47. | Heterogeneous integration solutions |
2.48. | Heterogeneous integration solutions |
2.49. | System on Chip (SOC) |
2.50. | System on Chip (SOC) (2) |
2.51. | Multi-Chip Module (MCM) |
2.52. | System in Package (SIP) |
2.53. | System on Package (SOP) |
2.54. | Comparison between SIP and SOP |
2.55. | PCB-Embedding Technology |
2.56. | PCB Embedding Technology - Active Chips |
2.57. | PCB Embedding Technology - Active Chips (continued) |
2.58. | PCB Embedding Technology - Cases |
2.59. | PCB Embedding Technology - Cases (continued) |
2.60. | Chip Embedding Technologies (CET) - Integrated Passive Device |
2.61. | Packaging technologies by interconnect technique |
2.62. | Interconnection technique |
2.63. | Interconnection technique - Wire Bond |
2.64. | Interconnection technique - Flip Chip |
2.65. | Interconnection technique - Wafer level packaging |
2.66. | Fan-out process flow |
2.67. | Interconnection technique - Interposer |
2.68. | Interposer Structure |
2.69. | Passive vs Active Interposer |
2.70. | Interposer alternative - Bridge |
2.71. | Interconnection technique - Technology benchmark |
2.72. | Die/Package stacking technologies |
2.73. | Die/Package stacking technologies - an overview |
2.74. | Package in Package (PIP) vs Package on Package (POP) |
2.75. | Die stacking |
2.76. | Differences between stacked packages and stacked dies |
2.77. | 2.5D and 3D IC Packaging |
2.78. | 2.5D IC Packaging |
2.79. | 3D IC Packaging technology |
2.80. | 3D IC Packaging |
3. | TECHNOLOGICAL DEEP DIVE INTO ADVANCED SEMICONDUCTOR PACKAGING TECHNOLOGIES FROM VARIOUS PLAYERS |
3.1. | Overview |
3.1.1. | Players in advanced semiconductor packaging and their solutions |
3.2. | TSMC's advanced semiconductor packaging solutions |
3.2.1. | TSMC 3DFabricTM packaging technologies overview |
3.2.2. | TSMC 2.5D packaging technology - CoWoS |
3.2.3. | TSMC 2.5D packaging technology - InFO |
3.2.4. | TSMC INFO technology - process flow |
3.2.5. | TSMC 2.5D packaging technology applications |
3.2.6. | TSMC 2.5D packaging technologies roadmap |
3.2.7. | TSMC 3D SoIC Technology |
3.2.8. | TSMC 3D SoIC development roadmap |
3.2.9. | Why scaling bump/bond pitch size is important? |
3.2.10. | Process of "bumpless" bonding - Cu bonding technologies |
3.2.11. | How bonding pitch size affects system performance |
3.2.12. | Roadmap of bond pitch scaling |
3.2.13. | Future high band width memory using SoIC technology |
3.2.14. | Thermal management for SoIC |
3.2.15. | Technology benchmark between 2.5D, 3D-IC, and SoIC |
3.2.16. | Combine 3D SoIC and 2.5D backend packaging technologies |
3.2.17. | N3XT Solution: 3D Monolithic integration |
3.2.18. | TSMC considers Packaging Facility in the US |
3.2.19. | Intel's advanced semiconductor packaging solutions |
3.2.20. | Intel advanced IC packaging profile |
3.2.21. | Intel Packaging technology roadmap |
3.2.22. | Intel EMIB (Embedded Multi-Die interconnect Bridge) |
3.2.23. | Products that use EMIB technology |
3.2.24. | EMIB Process flow |
3.2.25. | EMIB - power distribution path |
3.2.26. | EMIB key parameters |
3.2.27. | EMIB roadmap - bump size reduction |
3.2.28. | Intel Ponte Vecchio package teardown |
3.2.29. | Intel 3D Foveros |
3.2.30. | Intel 3D Foveros roadmap |
3.2.31. | Intel 3D Foveros ODI |
3.2.32. | Intel 3D Foveros Direct |
3.2.33. | Three key interconnect breakthrough from Intel |
3.2.34. | Intel interconnect technology - hybrid bonding |
3.2.35. | Intel interconnect technology - Zero Misaligned Via (ZMV) |
3.2.36. | Intel 3D packaging roadmap: Co-EMIB (2.5D+3D) |
3.2.37. | Intel Lakefield advanced semiconductor packaging |
3.2.38. | Intel's products that are/will be using 3D Foveros |
3.3. | SPIL's advanced semiconductor packaging solutions |
3.3.1. | SPIL Fan-Out Embedded Bridge (FOEB) Technology |
3.3.2. | SPIL FOEB Technology process flow |
3.3.3. | SPIL FOEB - Thermal and Warpage |
3.3.4. | SPIL FOEB vs 2.5D |
3.3.5. | SPIL FOEB vs Intel EMIB |
3.4. | Samsung's advanced semiconductor packaging solutions |
3.4.1. | Samsung advanced IC packaging profile |
3.4.2. | Samsung's advanced semiconductor packaging solutions |
3.4.3. | Samsung's technology roadmap for HPC |
3.4.4. | Samsung's advanced semiconductor packaging solutions for HPC |
3.4.5. | Samsung's X-Cube and I-Cube4 packaging schematic |
3.4.6. | Samsung RDL-first fan-out wafer level package (FOWLP) process flow |
3.4.7. | Samsung next generation high bandwidth memory: HBM3 |
3.4.8. | Samsung H-Cube advanced semiconductor packaging technology |
3.5. | Amkor's advanced semiconductor packaging solutions |
3.5.1. | Overview |
3.5.2. | Amkor's 2.5D TSV FCBGA |
3.5.3. | Summary of Amkor's 2.5D TSV technologies |
3.5.4. | Stacked substrate (2.5D packaging) from Amkor |
3.5.5. | High-Density Fan-Out (HDFO) solution from Amkor |
3.5.6. | Amkor's S-SWIFT packaging solution (1) |
3.5.7. | Amkor's S-SWIFT packaging solution (2) |
3.5.8. | Amkor - RDL layers development |
3.5.9. | Electrical characteristics vs different RDL solution |
3.5.10. | Amkor's S-SWIFT package development status |
3.5.11. | Amkor - 3D stacking |
3.5.12. | Amkor - Cu-Cu Hybrid bonding pathfinding on the way |
3.6. | ASE's advanced semiconductor packaging solutions |
3.6.1. | ASE 2.5D technologies - FOCoS |
3.6.2. | ASE FOCoS process flow (1) |
3.6.3. | ASE FOCoS process flow (2) |
3.6.4. | Pros and Cons of FOCoS chip last |
3.6.5. | ASE FOCoS chip last package characteristic |
3.7. | IMEC advanced semiconductor packaging solution |
3.7.1. | Imec's Flip Chip on FOWLP |
3.7.2. | Flip Chip on FOWLP - Process flow |
3.7.3. | Flip Chip on FOWLP - challenges |
3.7.4. | 3D Integration technology landscape |
4. | ADVANCED SEMICONDUCTOR PACKAGING - SUPPLY CHAIN AND PLAYERS |
4.1. | Overview |
4.1.1. | Players in advanced semiconductor packaging by geography |
4.1.2. | HPC chip supply chain analysis |
4.1.3. | Investment in advanced semiconductor packaging by companies |
4.2. | Chiplet |
4.2.1. | What is chiplet technology |
4.2.2. | Why chiplet technology |
4.2.3. | Benefits of chiplet |
4.2.4. | AMD Chiplet performance vs cost |
4.2.5. | Chiplet integration - use cases |
5. | ADVANCED SEMICONDUCTOR PACKAGING FOR DIFFERENT MARKETS |
5.1. | High-performance computing (HPC) |
5.1.1. | Introduction to Data Center Equipment: Servers, Switches and Supervisors |
5.1.2. | Server Board Layout (1) |
5.1.3. | Server board Layout (2) |
5.1.4. | Determining the Relative Numbers of Data Center Equipment |
5.1.5. | Data Center Switch Players |
5.1.6. | Average Switch Port Numbers |
5.1.7. | Examples of switch architecture |
5.1.8. | Data Center Server Unit Forecast 2022-2033 (Shipment) |
5.1.9. | Total addressable data center CPU market forecast 2022-2033 (Shipment) |
5.1.10. | Total addressable data center accelerator market forecast 2022-2033 (Shipment) |
5.2. | Semiconductor packaging for CPUs in data center servers and switches |
5.2.1. | Intel vs AMD for Server CPUs |
5.2.2. | Advanced semiconductor packaging for Intel latest Xeon server CPU (1) |
5.2.3. | Advanced semiconductor packaging for Intel latest Xeon server CPU (2) |
5.2.4. | AMD chip semiconductor packaging roadmap |
5.2.5. | Options for Integrating Multiple Chips |
5.2.6. | AMD's semiconductor packaging choices for chiplet integration |
5.2.7. | AMD Stacked 3D V-Cache technology for server CPU (1) |
5.2.8. | AMD Stacked 3D V-Cache technology for server CPU (2) |
5.2.9. | Future packaging trend for chiplet server CPU |
5.2.10. | Data center CPU: advanced semiconductor packaging unit forecast 2022-2033 (Shipment) |
5.3. | Semiconductor packaging for accelerators in data center servers and switches |
5.3.1. | Accelerators in servers |
5.3.2. | Server board layout - with accelerators (1) |
5.3.3. | Server board layout - with accelerators (2) |
5.4. | GPUs as data center accelerators |
5.4.1. | Computer memory hierarchy |
5.4.2. | HBM vs DDR for computing (1) |
5.4.3. | Drawbacks of High Bandwidth Memory (HBM) |
5.4.4. | Summary of HBM vs DDR |
5.4.5. | HBM vs DDR for computing - market trend |
5.4.6. | Approaches to package HBM and GPU |
5.4.7. | AMD new server GPU featuring new semiconductor packaging approach |
5.4.8. | AMD Elevated fanout bridge 2.5D |
5.4.9. | AMD patents GPU chiplet design for future graphics cards |
5.4.10. | AMD GPU memory choice for different applications |
5.4.11. | NVIDIA GPU for data centers |
5.4.12. | Computing modules with HBM (1) |
5.4.13. | Computing modules with HBM (2) |
5.4.14. | Intel Ponte Vecchio packaging insights |
5.5. | FPGA as data center accelerators |
5.5.1. | Server board layout - with FPGA accelerators |
5.5.2. | Intel FPGA packaging |
5.5.3. | Xilinx FPGA packaging |
5.5.4. | High-end commercial chips based on advanced semiconductor packaging technology (1) |
5.5.5. | High-end commercial chips based on advanced semiconductor packaging technology (2) |
5.5.6. | Summary |
5.5.7. | Logic-memory moving from 2D to 3D packaging |
5.5.8. | Data center accelerator: advanced semiconductor packaging unit forecast 2022-2033 (shipment) |
5.6. | Advanced semiconductor packaging in automotive |
5.6.1. | Future ADAS/Autonomous driving systems: requirements, actions, and current challenges |
5.6.2. | Three transformational pillars in automotive electronics |
5.7. | Autonomous vehicles (AVs) - an overview |
5.7.1. | Why Automate Cars? |
5.7.2. | The Automation Levels in Detail |
5.7.3. | Functions of Autonomous Driving at Different Levels |
5.7.4. | The European Commission's Roadmap to Autonomy |
5.7.5. | Autonomous Vehicle = Electric Vehicle? |
5.7.6. | Typical Sensor Suite for Autonomous Cars |
5.7.7. | What is Sensor Fusion? |
5.7.8. | Evolution of Sensor Suite from Level 1 to Level 4 |
5.7.9. | The Coming Flood of Data in Autonomous Vehicles |
5.7.10. | High demand for computing power in autonomous vehicles |
5.7.11. | Semiconductor Content Increase in AVs |
5.7.12. | Semiconductor Content Increase in EVs |
5.7.13. | Horizon Robotics: the Chinese Embedded AI Chip Unicorn |
5.8. | Autonomous driving platform - processors and chip packaging |
5.8.1. | The primary differentiators for AVs will be chip design and software |
5.8.2. | Autonomous driving platform - processors and packaging roadmap (1) |
5.8.3. | Autonomous driving platform - processors and packaging roadmap (2) |
5.8.4. | Chip design and packaging choice for AV computing processers from different suppliers |
5.8.5. | NVIDIA's AV computing modules for L5 automotive |
5.8.6. | Self-driving computing module packaging challenges |
5.8.7. | L4+ Autonomous vehicles sales forecast 2022-2045 |
5.8.8. | Total addressable ADAS processor & accelerator sales market for L4+ Autonomous vehicles forecast 2022-2045 |
5.8.9. | 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045 |
5.8.10. | 3D advanced semiconductor packaging unit sales for L4+ Autonomous vehicles forecast 2022-2045 |
5.9. | Transformation of AV chip supply chain |
5.9.1. | VW and Ford In-House Chip Design |
5.9.2. | Stellantis Design Chips with Foxconn |
5.9.3. | Nvidia Autonomous Development Kit |
5.9.4. | Nvidia - Daimler |
5.9.5. | BMW |
5.9.6. | Qualcomm |
5.9.7. | Xilinx (AMD brand) |
5.9.8. | Summary of Some Current Supply Relationships |
5.9.9. | Future Chip Supply Summarised |
5.9.10. | Autonomous Vertical Integration |
5.9.11. | Expect Supply Chain to Consolidate with Increased Automation |
5.10. | Autonomous - packaging for sensors and power modules |
5.10.1. | Autonomous - packaging for sensors and power modules |
5.10.2. | Packaging for sensors in ADAS (1) |
5.10.3. | Packaging for sensors in ADAS(2) |
5.10.4. | Radar IC Packages |
5.11. | EV - power module packaging |
5.11.1. | Power Module Packaging Over the Generations |
5.12. | Package Materials & Innovations |
5.12.1. | Traditional Power Module Packaging |
5.12.2. | Module Packaging Material Dimensions |
5.12.3. | Advanced Wirebonding Techniques |
5.12.4. | Technology Evolution Beyond Al Wire Bonding |
5.13. | Substrates |
5.13.1. | The Choice of Ceramic Substrate Technology |
5.13.2. | AlN: Overcoming its Mechanical Weakness |
5.14. | Approaches to Substrate Metallisation |
5.14.1. | Approaches to Metallisation: DPC, DBC, AMB and Thick Film Metallisation |
5.14.2. | Direct Plated Copper (DPC): Pros and Cons |
5.14.3. | Double Bonded Copper (DBC): Pros and Cons |
5.14.4. | Active Metal Brazing (AMB): Pros and Cons |
5.14.5. | Ceramics: CTE Mismatch |
5.15. | Introduction to 5G |
5.15.1. | Evolution of mobile communications |
5.15.2. | Global snapshot of allocated/targeted 5G spectrum |
5.15.3. | 5G network deployment strategy |
5.15.4. | Two types of 5G: sub-6 GHz and mmWave |
5.15.5. | Low, mid-band 5G is often the operator's first choice to provide 5G national coverage |
5.15.6. | 5G commercial/pre-commercial services by frequency |
5.16. | 5G infrastructure |
5.16.1. | From 1G to 5G: the evolution of cellular network infrastructure |
5.16.2. | Different RAN architectures |
5.16.3. | Why splitting the baseband unit (BBU) is necessary in 5G |
5.16.4. | High and Low layer split of the 5G network |
5.16.5. | More functional splits to support diverse 5G use cases |
5.16.6. | Evolution of Open RAN functional split |
5.16.7. | Samsung's VRAN solution |
5.16.8. | Ericsson's cloud RAN solution |
5.16.9. | Open RAN deployment based on commercial off-the-shelf (COTS) hardware |
5.16.10. | Ultra low latency networks require accelerator card |
5.16.11. | Open RAN infrastructure arrangement |
5.16.12. | 5G radio design trend |
5.16.13. | Trends in 5G antennas: active antennas and massive MIMO |
5.16.14. | Massive MIMO (mMIMO) |
5.16.15. | Antenna array architectures for beamforming |
5.16.16. | Software defined radio (SDR) |
5.16.17. | Block diagram of MIMO antenna array system |
5.16.18. | Integration of digital frontend with transceivers |
5.16.19. | Si design for Open RAN radio (Analog Devices case) |
5.16.20. | Marvell baseband Si for 5G Open RAN radio |
5.16.21. | Marvell SoC for 5G networks (2) |
5.16.22. | Xilinx's Si solution for 5G radio unit (1) |
5.16.23. | Xilinx's Si solution for 5G radio unit (2) |
5.16.24. | End-to-End 5G Silicon Solutions from Intel |
5.16.25. | Intel's FPGA for 5G radio (1) |
5.16.26. | Intel's FPGA for 5G radio (2) |
5.16.27. | The intentions of 5G system vendors enter Si battleground (1) |
5.16.28. | The intentions of 5G system vendors enter Si battleground (2) |
5.16.29. | Key chipset players involved in the telecom infrastructure |
5.16.30. | 5G base station types: macro cells and small cells |
5.16.31. | 5G radios by MIMO size unit forecast 2022-2032 (Cumulative) |
5.16.32. | Estimating the total addressable market for advanced semiconductor packaging in 5G RAN infrastructure 2022-2032 (Cumulative) |
5.16.33. | Advanced semiconductor packaging unit for 5G RAN networks 2022-2032 (Cumulative) |
5.17. | 5G mmWave Antenna in Package (AiP) |
5.17.1. | Overview of challenges, trends and innovations for mmWave 5G devices |
5.17.2. | High frequency integration and packaging trend |
5.17.3. | Example: Qualcomm mmWave antenna module |
5.17.4. | High frequency integration and packaging: Requirement and Challenges |
5.17.5. | Three ways of mmWave antenna integration |
5.17.6. | Technology benchmark of antenna packaging technologies |
5.17.7. | AiP development trend |
5.17.8. | Two types of AiP structures |
5.17.9. | Two types of IC-embedded technology |
5.17.10. | University of Technology, Sydney: AME antennas in packages for 5G wireless devices |
5.17.11. | Additively manufactured antenna-in-package |
5.17.12. | Low loss materials is key for 5G mmWave AiP |
5.17.13. | Low loss materials for AiP: Five important metrics that impact the materials selection |
5.17.14. | Overview of low-loss materials for AiP |
5.17.15. | Choices of low-loss materials for 5G mmWave AiP |
5.17.16. | Key low loss materials suppliers landscape |
5.17.17. | Benchmark of commercialised low-loss organic laminates |
5.17.18. | Organic materials are still the mainstream choice for substrates in AiP |
5.17.19. | Benchmark of low loss materials for AiP |
5.17.20. | 5G AiP Summary |
5.18. | Advanced semiconductor packaging technologies for consumer electronics |
5.18.1. | Introduction |
5.18.2. | TSMC's HD fanout solutions for consumer electronics |
5.18.3. | Samsung's new galaxy smartwatch |
5.18.4. | Packaging choices for packaging application processor environment (APE) in consumer electronics (1) |
5.18.5. | Packaging choices for packaging application processor environment (APE) in consumer electronics (2) |
5.18.6. | 3D packaging for APE in consumer electronics |
5.18.7. | Future packaging trend for APE in consumer electronics |
5.18.8. | Unit sales forecast for smartphones/tablets/smartwatches/AR/VR/MR 2022-2033 |
5.18.9. | Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (1) |
5.18.10. | Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (2) |
5.18.11. | Advanced semiconductor packaging unit forecast for APE in consumer electronics remarks |
5.18.12. | Apple's M1 ultra for workstations uses TSMC's fan-out technologies |
5.18.13. | AMD Stacked 3D V-Cache technology for consumer desktop CPU |
5.18.14. | Intel mobile SoC for laptops (Lakefield) advanced semiconductor packaging |
5.18.15. | Advanced semiconductor packaging in Intel's next generation CPU Meteor Lake |
5.18.16. | Global PC shipment forecast 2022-2033 |
5.18.17. | Advanced semiconductor packaging units in PC forecast 2022-2033 (1) |
5.18.18. | Advanced semiconductor packaging units in PC forecast 2022-2033 (2) |
6. | FORECAST SUMMARY |
6.1. | Data Center Server Unit Forecast 2022-2033 (Shipment) |
6.2. | Total addressable data center CPU market forecast 2022-2033 (Shipment) |
6.3. | Data center CPU: advanced semiconductor packaging unit forecast 2022-2033 (Shipment) |
6.4. | Total addressable data center accelerator market forecast 2022-2033 (Shipment) |
6.5. | Data center accelerator: advanced semiconductor packaging unit forecast 2022-2033 (shipment) |
6.6. | Future ADAS/Autonomous driving systems: requirements, actions, and current challenges |
6.7. | Three transformational pillars in automotive electronics |
6.8. | L4+ Autonomous vehicles sales forecast 2022-2045 |
6.9. | Total addressable ADAS processor & accelerator sales market for L4+ Autonomous vehicles forecast 2022-2045 |
6.10. | 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045 |
6.11. | 3D advanced semiconductor packaging unit sales for L4+ Autonomous vehicles forecast 2022-2045 |
6.12. | Unit sales forecast for smartphones/tablets/smartwatches/AR/VR/MR 2022-2033 |
6.13. | Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (1) |
6.14. | Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (2) |
6.15. | Global PC shipment forecast 2022-2033 |
6.16. | Advanced semiconductor packaging units in PC forecast 2022-2033 (1) |
6.17. | Advanced semiconductor packaging units in PC forecast 2022-2033 (2) |
6.18. | 5G radios by MIMO size unit forecast 2022-2032 (Cumulative) |
6.19. | Estimating the total addressable market for advanced semiconductor packaging in 5G RAN infrastructure 2022-2032 (Cumulative) |
6.20. | Advanced semiconductor packaging unit for 5G RAN networks 2022-2032 (Cumulative) |
Slides | 444 |
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Forecasts to | 2033 |
ISBN | 9781915514097 |