บรรจุภัณฑ์เซมิคอนดักเตอร์ขั้นสูง 2025-2035: การคาดการณ์, เทคโนโลยี, การใช้งาน
การบูรณาการที่แตกต่างกัน, AI, HPC, ศูนย์ข้อมูล, การพยากรณ์ตลาดบรรจุภัณฑ์เซมิคอนดักเตอร์, เสาอากาศในแพ็คเกจ, 2.5D, 3D, Fan Out, FOWLP, FOPLP, Through Si-Via, บรรจุภัณฑ์แก้ว, เลนส์ร่วมบรรจุภัณฑ์, RDL (ชั้นการกระจายใหม่), การพันธะแบบไฮบริด
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The evolution of semiconductor packaging technologies
Semiconductor packaging has evolved from traditional 1D PCB designs to cutting-edge 3D hybrid bonding at the wafer level. This advancement allows for interconnect pitches in the single-digit micrometer range and bandwidths up to 1000 GB/s, all while maintaining high energy efficiency. Central to advanced semiconductor packaging technologies are 2.5D packaging—where components are positioned side by side on an interposer—and 3D packaging, which involves stacking active dies vertically. These technologies are critical for the future of HPC systems.
2.5D packaging technologies involve various interposer materials, each offering distinct advantages and drawbacks. Silicon (Si) interposers, which include full passive Si wafers and localized Si bridges, are known for facilitating the finest routing features, making them ideal for high-performance computing. However, they come with high costs in both materials and manufacturing, and face limitations in packaging area. To mitigate these issues, the use of localized Si bridges is increasing, strategically utilizing silicon where fine features are essential and addressing area constraints.
Organic interposers, which use a fan-out molding compound, offer a more cost-effective alternative to silicon. They have a lower dielectric constant, which reduces RC delay in the package. Despite these benefits, organic interposers struggle to achieve the same level of interconnect feature reduction as silicon-based packages, limiting their adoption in high-performance computing applications.
Glass interposers have gained significant interest, particularly after Intel's recent unveiling of a glass-based test vehicle package. Glass offers advantageous properties such as a tunable Coefficient of Thermal Expansion (CTE), high dimensional stability, a smooth as well as flat surface, and the ability to enable panel manufacturing, making it a promising candidate for interposers with routing features that could rival silicon. However, the main drawback of glass interposers is the immature ecosystem and the current lack of large-scale production capabilities, in addition to its technical challenges. As the ecosystem matures and production capabilities improve, glass-based technologies in semiconductor packaging may see further growth and adoption.
Regarding 3D packaging technologies, Cu-Cu bumpless hybrid bonding is emerging as a leading innovation. This advanced technique creates permanent interconnections by combining a dielectric material, such as SiO2, with embedded metal (Cu). Cu-Cu hybrid bonding can achieve pitches below 10 micrometers, typically in the single-digit micrometer range, which is a significant improvement over conventional microbump technology, which has a bump pitch of around 40-50 micrometers. The benefits of hybrid bonding include increased I/O, higher bandwidth, improved 3D vertical stacking, enhanced power efficiency, and reduced parasitics and thermal resistance due to the absence of underfill. However, this technique is complex to manufacture and comes with higher costs.
Overview of interconnection technique in semiconductor packaging. Source: Advanced Semiconductor Packaging 2025-2035
The 2.5D and 3D packaging technologies encompass various packaging techniques. In 2.5D packaging, the choice of interposer material categorizes it into Si-based, Organic-based, and glass-based interposers, as illustrated in the figure above. Meanwhile, in 3D packaging, the evolution of microbump technology aims for smaller pitch dimensions. However, achieving single-digit pitch dimensions today is made possible through the adoption of hybrid bonding technology, a method that directly connects Cu-Cu, indicating a significant advancement in the field.
Key trends in 2.5D and 3D packaging development to watch:
- Larger Interposer Areas
IDTechEx has previously predicted that 2.5D silicon bridge solutions will soon replace silicon interposers as the primary choice for packaging HPC chips, due to the limitations of silicon interposers, which struggles to exceed 3x reticle sizes. TSMC, a key provider of 2.5D silicon interposers to NVIDIA and other major HPC developers like Google and Amazon, recently announced high-volume production of its first-generation CoWoS_L at 3.5x reticle size. IDTechEx expects this trend to continue, with further advancements explored in their report covering key players.
- Panel-Level Packaging
Panel-level packaging has become a significant focus, as highlighted at Semicon Taiwan 2024. This packaging method allows for larger interposers and helps reduce costs by enabling the production of more packages simultaneously. Despite its potential, challenges such as warpage management still need to be addressed. Its growing prominence reflects the increasing demand for larger and more cost-effective interposers.
- Glass Interposers
Glass is emerging as a strong candidate for enabling fine routing, comparable to silicon, with added benefits like tunable coefficient of thermal expansion (CTE) and improved reliability. Glass interposers are also compatible with panel-level packaging, offering the potential for high-density routing at a more manageable cost, making them a promising solution for future packaging technologies.
- Hybrid Bonding for HBMs
3D copper-copper (Cu-Cu) hybrid bonding is a critical technology for enabling ultra-fine pitch vertical interconnects between chips. This technology has already been used in several high-end server products, including AMD's EPYC for stacking SRAM and CPUs, and the MI300 series for stacking CPU/GPU tiles on I/O tiles. Hybrid bonding is expected to play a pivotal role in future HBM advancements, particularly for DRAM stacks beyond 16-Hi or 20-Hi layers.
- Co-Packaged Optics (CPO)
Optical interconnect technology has gained considerable traction, driven by the growing need for higher data throughput alongside improved power efficiency. Co-packaged optics (CPO) is emerging as a key solution to enhance I/O bandwidth and reduce energy consumption. Optical communication offers multiple advantages over traditional electrical transmission, including lower signal degradation over distance, reduced susceptibility to crosstalk, and significantly higher bandwidth. These benefits make CPO an ideal fit for data-intensive, power-efficient HPC systems.
Key markets to watch
The primary market driving the development of 2.5D and 3D packaging technologies is undoubtedly the high-performance computing (HPC) sector. These advanced packaging methods are crucial in overcoming the limitations of Moore's law, enabling more transistors, memory, and interconnections within a single package. The disaggregation of chips also allows for optimal process node utilization across different functional blocks, such as separating I/O tiles from processing tiles, further enhancing efficiency.
Beyond HPC, other markets are poised for growth through the adoption of advanced packaging technologies. In the 5G and 6G sectors, innovations like antenna-in-package and cutting-edge chip solutions will shape the future of radio access network (RAN) architectures. Autonomous vehicles will also benefit, as these technologies support the integration of sensor suites and computing units to process large volumes of data while ensuring safety, reliability, compactness, power and thermal management, and cost-effectiveness.
Consumer electronics—including smartphones, smartwatches, AR/VR devices, PCs, and workstations—though more cost-conscious, are increasingly focused on handling more data within smaller spaces. Advanced semiconductor packaging will play a key role in this trend, though the packaging methods will differ from those used in HPC. IDTechEx provides in-depth analysis of these industries, examining how advanced packaging technologies will impact them and offering market forecasts.
Key markets for advanced semiconductor packaging. Source: Advanced Semiconductor Packaging 2025-2035
What is in this report?
The report "Advanced Semiconductor Packaging 2025-2035" thoroughly explores the latest innovations in semiconductor packaging technology, covering key technical trends, analyzing the value chain, evaluating major players, and providing detailed market forecasts.
Recognizing the crucial role of advanced semiconductor packaging as the foundation for next-generation ICs, the report focuses on its applications in key markets such as AI and data centers, 5G, autonomous vehicles, and consumer electronics. Leveraging IDTechEx's expertise in these sectors, the report delivers a comprehensive understanding of the impact and future trajectory of advanced semiconductor packaging in these critical fields.
Key aspects in this report:
Exploring Technology Trends and Manufacturers in Advanced Semiconductor Packaging:
- Explore advanced semiconductor packaging evolution, addressing transistor IC challenges. Examine how chiplet concepts and heterogeneous integration propel advanced packaging adoption.
- Analyze Packaging Technologies: Segment by interposer material (Si, Glass, Organic), covering roadmaps, benchmarks, applications, players, and manufacturing barriers.
- Company Analysis: In-depth examination of key companies, assessing solutions, clientele, applications, and technology roadmap.
- Key Markets: Provide detailed overviews for critical markets - high-performance computing, autonomous vehicles, 5G, and consumer electronics.
- Case Studies: Showcase various industry applications of advanced semiconductor packaging.
- Supply Chain & Models: Analyze supply chain dynamics and business models in this evolving landscape.
10-year Granular Market Forecasts & Analysis:
- Data Center Server Unit Forecast 2023-2035 (Shipment)
- Data Center CPU: Advanced Semiconductor Packaging Forecast 2023-2035 (Shipment)
- Data Center Accelerator: Semiconductor Packaging Forecast 2023-2035 (Shipment)
- 2.5D Semiconductor Packaging for L4+ Autonomous Vehicles 2023-2045
- 3D Semiconductor Packaging for L4+ Autonomous Vehicles 2023-2045
- Consumer Electronics Unit Sales Forecast 2023-2035 (Smartphones/Tablets/Smartwatches/AR/VR/MR)
- Advanced Semiconductor Packaging Forecast for APE in Consumer Electronics 2023-2035
- Global PC Shipment Forecast 2023-2035
- Advanced Semiconductor Packaging in PC Forecast 2023-2035
- 5G Radios by MIMO Size Unit Forecast 2023-2035
- Advanced Semiconductor Packaging for 5G RAN Networks 2023-2035
- Total CPO market forecast in revenue 2023-2035
| Report Metrics | Details |
|---|---|
| Historic Data | From 2022 |
| Forecast Period | 2024 - 2035 |
| Forecast Units | Millions |
| Regions Covered | Worldwide |
Analyst access from IDTechEx
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Further information
If you have any questions about this report, please do not hesitate to contact our report team at research@IDTechEx.com or call one of our sales managers:
ASIA: +44 1223 810259
| 1. | EXECUTIVE SUMMARY |
| 1.1. | Advanced semiconductor packaging technologies - our scope |
| 1.2. | Why advanced semiconductor packaging now? |
| 1.3. | Four key drivers for advanced semiconductor packaging technologies |
| 1.4. | Evolution roadmap of semiconductor packaging |
| 1.5. | Overview of interconnection technique in semiconductor packaging |
| 1.6. | Key metrics for advanced semiconductor packaging performance |
| 1.7. | Tech development trend for 2.5D packaging |
| 1.8. | Wafer level vs Panel level Fan-Out: Key differences |
| 1.9. | Key trends in fan-out packaging |
| 1.10. | Evolution of bumping technologies |
| 1.11. | 3D Bumpless Cu-Cu hybrid bonding |
| 1.12. | Challenges in 3D Hybrid bonding |
| 1.13. | Advanced Semiconductor packaging - technology benchmark overview (1) |
| 1.14. | Advanced Semiconductor packaging - technology benchmark overview (2) |
| 1.15. | Advanced semiconductor packaging technology - highlights from key players - 1 |
| 1.16. | Advanced semiconductor packaging technology - highlights from key players - 2 |
| 1.17. | Key markets for advanced semiconductor packaging |
| 1.18. | HPC chips integration trend - overview |
| 1.19. | Chiplet roadmap for HPC |
| 1.20. | How future HPC platform would look like? |
| 1.21. | Key trend of optical transceiver packaging in high-end data centers |
| 1.22. | 2D to 3D EIC/PIC integration options |
| 1.23. | Challenges and future potential of CPO technology |
| 1.24. | Total CPO market |
| 1.25. | Key highlights regarding HBM development from Semicon Taiwan 2024 |
| 1.26. | HBM4 race: SK Hynix vs Samsung |
| 1.27. | Overview of antenna packaging technologies vs operational frequency |
| 1.28. | Benchmarking three antenna packaging technologies |
| 1.29. | Commercialized high density fan-out packaging solutions |
| 1.30. | Data center CPU: advanced semiconductor packaging unit forecast 2025-2035 (shipment) |
| 1.31. | Data center accelerator: advanced semiconductor packaging unit forecast 2023-2035 (shipment) |
| 1.32. | 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045 |
| 1.33. | Advanced semiconductor packaging unit forecast for APE (application processor environment) in consumer electronics 2023-2035 (1) |
| 1.34. | Advanced semiconductor packaging units in PC forecast 2023-2035 (1) |
| 1.35. | Advanced semiconductor packaging unit for 5G RAN networks 2023-2035 (cumulative) |
| 2. | INTRODUCTION TO ADVANCED SEMICONDUCTOR PACKAGING |
| 2.1. | Challenges in transistor scaling |
| 2.1.1. | The growing demand for data computing power |
| 2.1.2. | Fundamentals of abundant data computing system |
| 2.1.3. | Key parameter of growth for processor and memory (1) |
| 2.1.4. | Key parameter of growth for processor and memory (2) |
| 2.1.5. | Memory bandwidth deficit |
| 2.1.6. | Four key area of growth for abundance data computing system |
| 2.1.7. | Key parameters for transistor device scaling |
| 2.1.8. | Evolution of transistor device architectures |
| 2.1.9. | Scaling technology roadmap overview |
| 2.1.10. | Semiconductor foundries and their roadmap |
| 2.1.11. | The economics of scaling |
| 2.1.12. | Challenges in transistor scaling |
| 2.1.13. | The solution forward: chiplet + advanced semiconductor packaging |
| 2.2. | The rise of Chiplet |
| 2.2.1. | The rise of chiplets |
| 2.2.2. | What is chiplet technology |
| 2.2.3. | Use cases and benefits |
| 2.2.4. | AMD Chiplet performance vs cost |
| 2.2.5. | Advanced semiconductor packaging: The chiplet enabler |
| 2.3. | The rise of Advanced Semiconductor Packaging technologies |
| 2.3.1. | General electronic packaging - an overview |
| 2.3.2. | Advanced semiconductor packaging - an overview |
| 2.3.3. | The rise of advanced semiconductor packaging |
| 2.3.4. | The challenges of advanced semiconductor packaging and its challenges |
| 2.3.5. | Four key drivers for advanced semiconductor packaging technologies |
| 2.3.6. | Key figures of merit of advanced semiconductor packaging technologies |
| 3. | ADVANCED SEMICONDUCTOR PACKAGING TECHNOLOGIES: DEEP-DIVE INTO 2.5D AND 3D PACKAGING |
| 3.1. | Four key factors of advanced semiconductor packaging |
| 3.2. | Advanced semiconductor packaging technologies - overview of technologies |
| 3.2.1. | Evolution roadmap of semiconductor packaging |
| 3.2.2. | Semiconductor packaging - an overview of technology |
| 3.2.3. | Overview of interconnection technique in semiconductor packaging |
| 3.2.4. | Moving towards 3D packaging: Pros and Cons |
| 3.2.5. | Interconnection technique - Wire Bond |
| 3.2.6. | Interconnection technique - Flip Chip |
| 3.2.7. | Interconnection technique - Interposer |
| 3.2.8. | Passive vs active interposer |
| 3.2.9. | Interconnection technique - technology benchmark |
| 3.3. | 2.5D packaging |
| 3.3.1. | 2.5D packaging - introduction |
| 3.3.2. | 2.5D Packaging - benefits and challenges |
| 3.3.3. | Overview 2.5D semiconductor packaging technology |
| 3.4. | 2.5D Si-based packaging |
| 3.4.1. | 2.5D packaging that involves Si as interconnect |
| 3.4.2. | Interposer Structure |
| 3.4.3. | Through Si Via (TSV) - now and the future |
| 3.4.4. | Through-Si-Via (TSV) fabrication process flow |
| 3.4.5. | Through-Si-Via (TSV) fabrication method |
| 3.4.6. | SiO2 RDL fabrication |
| 3.4.7. | RDL layer thickness |
| 3.4.8. | 2.5D Si interposer: Complete process overview |
| 3.4.9. | Si Bridge |
| 3.4.10. | Si interposer vs Si bridge benchmark |
| 3.4.11. | Case studies |
| 3.4.12. | Players that have 2.5D Si-based packaging solutions |
| 3.4.13. | Developing trend for 2.5D Si-based packaging |
| 3.4.14. | Packaging challenges in 2.5D |
| 3.5. | 2.5D Organic-based packaging |
| 3.5.1. | 2.5D packaging - high density fan-out packaging |
| 3.5.2. | Two types of fan-out: Panel level |
| 3.5.3. | Two types of fan-out: Wafer level |
| 3.5.4. | Wafer level vs Panel level Fan-Out: Key differences |
| 3.5.5. | Key trends in fan-out packaging |
| 3.5.6. | Fan-out packaging process overview |
| 3.5.7. | Fan-out chip-first process flow |
| 3.5.8. | Fan-out chip-last process flow |
| 3.5.9. | Fan-out chip-last RDL formation - development trend |
| 3.5.10. | Challenges in future fan-out process |
| 3.5.11. | Limitations in organic substrate |
| 3.5.12. | Organic RDL |
| 3.5.13. | Key Factors to Consider When Choosing material for Electronic Interconnects |
| 3.5.14. | Electronic interconnects: SiO2 vs Organic dielectric |
| 3.5.15. | Key parameters for organic RDL materials for next generation 2.5D fan-out packaging |
| 3.6. | 2.5D glass-based packaging |
| 3.6.1. | Benefits of glass |
| 3.6.2. | Roles of glass in semiconductor packaging |
| 3.6.3. | Value proposition of glass as core material for 2.5D package |
| 3.6.4. | Overcoming Limitations of Si interposers with Glass |
| 3.6.5. | Glass core as interposer for advanced semiconductor packaging |
| 3.6.6. | Glass core (interposer) package - process flow |
| 3.6.7. | TGV - Player and products benchmark |
| 3.6.8. | TGV of >15 aspect ratio |
| 3.6.9. | Samtec TGV |
| 3.6.10. | Absolic's glass packaging solution |
| 3.6.11. | Achieving 2/2 um L/S on glass substrate |
| 3.6.12. | Eight metal layer RDL on glass process flow |
| 3.6.13. | <3 um micro via |
| 3.6.14. | 3D Glass Panel Embedding (GPE) package |
| 3.6.15. | 3D Glass Panel Embedding (GPE) package- process flow |
| 3.6.16. | Glass vs molding compound |
| 3.6.17. | GPE vs Glass interposer - 1 |
| 3.6.18. | GPE vs Glass interposer - specification benchmark |
| 3.6.19. | GPE vs Glass interposer - process benchmark |
| 3.6.20. | Glass - thermal management |
| 3.6.21. | RDL dielectrics on glass substrate |
| 3.6.22. | Glass interposer - more demonstrated case studies |
| 3.6.23. | Challenges of glass packaging |
| 3.7. | Technology Benchmark: Si vs Organic vs Glass |
| 3.7.1. | Benchmark of materials for interposer |
| 3.7.2. | Interposer material supplier landscape |
| 3.7.3. | Advanced Semiconductor packaging - technology benchmark overview (1) |
| 3.7.4. | Advanced Semiconductor packaging - technology benchmark overview (2) |
| 3.8. | 3D Hybrid bonding |
| 3.8.1. | Conventional 3D packaging (No TSVs) |
| 3.8.2. | Advanced 3D Packaging (W/ TSVs) |
| 3.8.3. | Advanced 3D Packaging |
| 3.8.4. | Evolution of bumping technologies |
| 3.8.5. | µ bump for advanced semiconductor packaging |
| 3.8.6. | Challenges in scaling bumps |
| 3.8.7. | Bumpless Cu-Cu hybrid bonding |
| 3.8.8. | Enhancing Energy Efficiency Through Hybrid Bonding Pitch Scaling |
| 3.8.9. | Cu-Cu hybrid bonding manufacturing process flow |
| 3.8.10. | Three ways of Cu-Cu hybrid bonding |
| 3.8.11. | Technology benchmark between 2.5D, 3D micro bump, and 3D hybrid bonding |
| 3.8.12. | Performance benchmark of devices based on micro bumps vs Cu-Cu bumpless hybrid bonding |
| 3.8.13. | Overview of devices that make use of hybrid bonding |
| 3.8.14. | Challenges in 3D Hybrid bonding |
| 4. | ADVANCED SEMICONDUCTOR PACKAGING TECHNOLOGIES: PLAYER ANALYSIS |
| 4.1. | Overview |
| 4.1.1. | Business value chain in IC industry |
| 4.1.2. | Ecosystem/Business model in the IC industry |
| 4.1.3. | Role and advantages of players in advanced semiconductor packaging market |
| 4.1.4. | Players in advanced semiconductor packaging and their solutions |
| 4.2. | TSMC's advanced semiconductor packaging solutions |
| 4.2.1. | TSMC's advanced semiconductor packaging technology portfolio |
| 4.2.2. | TSMC 2.5D packaging technology - CoWoS |
| 4.2.3. | CoWoS - an update from TSMC at Semicon Taiwan 2024 |
| 4.2.4. | CoWoS - development progress and roadmap |
| 4.2.5. | Key development steps for CoWoS to meet future packaging performance |
| 4.2.6. | Challenges in large interposer manufacturing and its solutions |
| 4.2.7. | CoWoS-L |
| 4.2.8. | CoWoS_L process flow |
| 4.2.9. | Fabrication of Local Si Interconnect (LSI) |
| 4.2.10. | CoWoS-L key development features |
| 4.2.11. | Solutions to achieve > 5x reticle interposer area (1) |
| 4.2.12. | Solutions to achieve > 5x interposer area (2) |
| 4.2.13. | CoWoS-L > 5x reticle size test vehicle results |
| 4.2.14. | Solution to go beyond 9x reticle size? |
| 4.2.15. | InFO_SoW |
| 4.2.16. | CoW_SoW |
| 4.2.17. | Tesla's Dojo system-on-wafer (SoW) processor for AI training |
| 4.2.18. | TSMC CoWoS market |
| 4.2.19. | TSMC packaging facility overview |
| 4.2.20. | TSMC 2.5D packaging technology - InFO |
| 4.2.21. | TSMC 2.5D InFO packaging technologies roadmap |
| 4.2.22. | TSMC 2.5D packaging technology applications |
| 4.2.23. | TSMC 3D SoIC Technology |
| 4.2.24. | Roadmap of SoIC hybrid bonding scaling |
| 4.2.25. | How bonding pitch size affects system performance |
| 4.2.26. | TSMC SoIC-P (micro bump) roadmap |
| 4.2.27. | Key Applications of 3D SoIC packages |
| 4.2.28. | Combined 3D SoIC and 2.5D backend packaging technologies |
| 4.2.29. | iOIS - Integrated Optical Interconnection System from TSMC |
| 4.2.30. | Summary - TSMC advanced semiconductor packaging technology |
| 4.3. | Intel's advanced semiconductor packaging solutions |
| 4.3.1. | Intel's advanced semiconductor packaging technology portfolio |
| 4.3.2. | Introduction to Intel EMIB (Embedded Multi-Die interconnect Bridge) |
| 4.3.3. | EMIB process flow |
| 4.3.4. | EMIB process challenges |
| 4.3.5. | EMIB key parameters |
| 4.3.6. | EMIB bump size reduction roadmap |
| 4.3.7. | Products that use EMIB technology |
| 4.3.8. | Intel 3D FOVEROS technology |
| 4.3.9. | Intel 3D FOVEROS ODI |
| 4.3.10. | Intel's 3D FOVEROS roadmap highlights |
| 4.3.11. | Table of Intel's products that adopts 3D FOVEROS |
| 4.3.12. | Three key interconnect breakthroughs from Intel |
| 4.3.13. | Intel 3D FOVEROS Direct hybrid bonding - roadmap |
| 4.3.14. | FOVEROS Direct: Passive vs Active interposer |
| 4.3.15. | FOVEROS Direct: Base die orientation |
| 4.3.16. | Intel interconnect technology - Zero Misaligned Via (ZMV) |
| 4.3.17. | Intel 3D packaging roadmap: 3.5D (2.5D EMIB + 3D FOVEROS) |
| 4.3.18. | Intel advanced packaging roadmap overview |
| 4.3.19. | Intel glass packaging roadmap |
| 4.3.20. | Intel's test vehicle for glass packaging |
| 4.3.21. | Intel packaging sites |
| 4.3.22. | Summary - Intel advanced semiconductor packaging technology |
| 4.4. | Samsung's advanced semiconductor packaging solutions |
| 4.4.1. | Samsung's advanced semiconductor packaging technology portfolio |
| 4.4.2. | Overview of Samsung's targeted applications |
| 4.4.3. | Samsung Advanced Interconnection Technology (SAINT) |
| 4.4.4. | Samsung's AI solutions |
| 4.4.5. | Samsung's advanced semiconductor packaging roadmap |
| 4.4.6. | Samsung's 2.5D packaging solutions (I-Cube) |
| 4.4.7. | 2.5D Molded Interposer on Substrate (MIoS) package |
| 4.4.8. | Samsung's 2.5D packaging solutions (H-Cube) |
| 4.4.9. | Fan-out packaging portfolio |
| 4.4.10. | Samsung RDL-first fan-out wafer/panel level package |
| 4.4.11. | FOPLP for HPC products? |
| 4.4.12. | Samsung's 3D packaging solutions |
| 4.4.13. | Samsung's Cu-Cu bonding |
| 4.4.14. | Summary - Samsung advanced semiconductor packaging technology |
| 4.4.15. | OSAT's advanced semiconductor packaging technologies |
| 4.5. | ASE's advanced semiconductor packaging solutions |
| 4.5.1. | ASE 2.5D technologies - FOCoS |
| 4.5.2. | ASE's VIPack (Advanced packaging solutions for heterogeneous integration) |
| 4.5.3. | ASE Advanced Packaging Roadmap |
| 4.5.4. | ASE FOCoS process flow (1) |
| 4.5.5. | ASE FOCoS process flow (2) |
| 4.5.6. | FOCoS - Packaging spec benchmark |
| 4.5.7. | HVM products based on CL-FOCoS |
| 4.5.8. | Development Test Vehicle for HBM3 |
| 4.5.9. | FOCoS-CL Example and Spec |
| 4.5.10. | FOCoS-B (w/ and w/o TSVs) Examples and Spec - 1 |
| 4.5.11. | FOCoS-B (w/ and w/o TSVs) Examples and Spec - 2 |
| 4.5.12. | Pros and Cons of FOCoS chip last |
| 4.5.13. | 2.5D/3D TSV from ASE |
| 4.5.14. | RDL spec benchmark (FOCOS vs Bridge vs Si interposer) |
| 4.5.15. | FOPOP from ASE - process |
| 4.5.16. | Carrier utilization vs reticle size: Wafer vs Panel |
| 4.5.17. | ASE approach to panel |
| 4.5.18. | ASE 300mm Panel Process Overview |
| 4.5.19. | ASE 600 mm process |
| 4.5.20. | ASE's proposed fan-out solution for CPO packaging |
| 4.5.21. | Optical packaging process considerations for silicon photonics - ASE |
| 4.5.22. | SPIL's advanced semiconductor packaging solutions |
| 4.5.23. | SPIL's advanced packaging solutions |
| 4.5.24. | SPIL Fan-Out Embedded Bridge (FOEB) Technology |
| 4.5.25. | SPIL FOEB Technology process flow |
| 4.5.26. | SPIL FOEB - Thermal and warpage |
| 4.5.27. | SPIL FOEB-T |
| 4.5.28. | FO-EB-T Process flow |
| 4.5.29. | Performance benchmark: FOEB vs FOEB-T vs 2.5D Si interposer |
| 4.5.30. | SPIL's Fan-Out Embedded Bridge (FOEB) structure for PIC/EIC integration in CPO |
| 4.5.31. | SPIL FOEB vs Intel EMIB |
| 4.6. | Amkor's advanced semiconductor packaging solutions |
| 4.6.1. | Amkor advanced semiconductor packaging solutions |
| 4.6.2. | Amkor's 2.5D TSV FCBGA |
| 4.6.3. | Summary of Amkor's 2.5D TSV technologies |
| 4.6.4. | Stacked substrate (2.5D packaging) from Amkor |
| 4.6.5. | High-Density Fan-Out (HDFO) solution from Amkor |
| 4.6.6. | Amkor's S-SWIFT packaging solution (1) |
| 4.6.7. | Amkor's S-SWIFT packaging solution (2) |
| 4.6.8. | Amkor - RDL layers development |
| 4.6.9. | Electrical characteristics vs different RDL solution |
| 4.6.10. | Amkor's S-SWIFT package development status |
| 4.6.11. | Amkor - 3D stacking |
| 4.6.12. | Amkor - Cu-Cu Hybrid bonding pathfinding on the way |
| 5. | ADVANCED SEMICONDUCTOR PACKAGING TECHNOLOGIES: APPLICATIONS |
| 5.1. | Packaging trend for key markets |
| 5.2. | High Performance Computing (HPC) Chips |
| 5.2.1. | Chapter introduction |
| 5.2.2. | Challenges for next generation AI chips |
| 5.2.3. | The rise and the challenges of LLM |
| 5.2.4. | Fundamentals of abundance data computing system |
| 5.2.5. | State-of-the-art high-end AI chips |
| 5.2.6. | Evolution of AI compute system architecture |
| 5.2.7. | NVIDIA and AMD solutions for next-gen AI |
| 5.2.8. | The next step forward to improve system bandwidth |
| 5.2.9. | How advanced semiconductor packaging can address the challenges? |
| 5.2.10. | Why traditional Moore's Law scaling cannot meet the growing needs for HPC |
| 5.2.11. | Key Factors affecting HPC datacenter performance |
| 5.2.12. | Advanced semiconductor packaging path for HPC |
| 5.2.13. | Trend in package integration |
| 5.2.14. | HPC chips integration trend - overview |
| 5.2.15. | HPC chips integration trend - explanation |
| 5.3. | Co-Packaged Optics |
| 5.3.1. | Silicon photonics |
| 5.3.2. | Overview of key challenges in data center architectures |
| 5.3.3. | Advancements in Switch IC Bandwidth and the Need for Co-Packaged Optics (CPO) Technology |
| 5.3.4. | Key trend of optical transceiver in high-end data centers |
| 5.3.5. | Heterogeneous integration and Co-Packaged Optics (CPO) |
| 5.3.6. | What is an Optical Engine (OE) |
| 5.3.7. | Design decisions for CPO compared to Pluggables |
| 5.3.8. | Key CPO applications: Network switch and computing optical I/O |
| 5.3.9. | Overview of CPO Packaging Technologies |
| 5.3.10. | Overview of Interconnection Technique in Semiconductor Packaging |
| 5.3.11. | EIC/PIC integration by advanced interconnect technique |
| 5.3.12. | 2D to 3D EIC/PIC integration options |
| 5.3.13. | Benchmark table of different packaging technologies for EIC/PIC |
| 5.3.14. | Pros and Cons of 2D integration of EIC/PIC |
| 5.3.15. | Pros and Cons of 2.5D integration of EIC/PIC |
| 5.3.16. | Pros and Cons of 3D hybrid integration of EIC/PIC |
| 5.3.17. | Pros and Cons of 3D monolithic integration of EIC/PIC |
| 5.3.18. | Three types of CPO + XPU/switch ASIC packaging structures |
| 5.3.19. | Examples of packaging a 3D optical engine with an IC |
| 5.3.20. | 3.2 Tb/s CPO module defined by the Optical Internetworking Forum (OIF) - 1 |
| 5.3.21. | Challenges and future potential of CPO technology |
| 5.3.22. | CPO Demonstration products benchmarked |
| 5.3.23. | Total CPO market |
| 5.4. | High Bandwidth Memory (HBM) |
| 5.4.1. | Computer memory hierarchy |
| 5.4.2. | HBM - device architecture and its functionalities |
| 5.4.3. | HBM vs DDR for computing (1) |
| 5.4.4. | Drawbacks of High Bandwidth Memory (HBM) |
| 5.4.5. | Summary of HBM vs DDR |
| 5.4.6. | HBM vs DDR for computing - market trend |
| 5.4.7. | HBM generations - specification benchmark |
| 5.4.8. | Key highlights regarding HBM development from Semicon Taiwan 2024 |
| 5.4.9. | HBM Packaging |
| 5.4.10. | HBM packaging challenges - Thinning DRAM wafer |
| 5.4.11. | HBM packaging challenges - bonding technologies |
| 5.4.12. | HBM packaging - limitations of micro-bump |
| 5.4.13. | HBM packaging transition to hybrid bonding |
| 5.4.14. | Benchmark HBM performance: microbump vs hybrid bonding |
| 5.4.15. | Approaches to package HBM and GPU |
| 5.4.16. | SK Hynix |
| 5.4.17. | SK Hynix: HBM stacking technology roadmap |
| 5.4.18. | HBM Packaging: TC-NCF vs MR-MUF |
| 5.4.19. | 8-Hi HBM using MR-MUF |
| 5.4.20. | SK Hynix: HBM thermal management roadmap |
| 5.4.21. | Challenges for going beyond 16 Hi |
| 5.4.22. | Stacking DRAMs using hybrid bonding - a study from SK Hynix |
| 5.4.23. | C2W bonding for next generation HBM |
| 5.4.24. | Samsung |
| 5.4.25. | Packaging for high bandwidth memory (HBM) |
| 5.4.26. | Hybrid bonding for HBM packaging - Samsung's findings and roadmap |
| 5.4.27. | Hybrid bonding for HBM packaging - Samsung's findings and roadmap continue |
| 5.4.28. | HBM4 race: Samsung vs SK Hynix |
| 5.5. | HPC system Packaging Strategies by Leading Companies |
| 5.5.1. | NVIDIA |
| 5.5.2. | NVIDIA data center GPUs based on advanced semiconductor packaging |
| 5.5.3. | NVIDIA Blackwell GPU |
| 5.5.4. | Closer look into NVIDIA's state-of-the-art AI system |
| 5.5.5. | Number of Cu wires in current AI system Interconnects |
| 5.5.6. | Nvidia's connectivity choices: Copper vs. optical for high-bandwidth systems |
| 5.5.7. | Moving from Cu to optical interconnects for a high-end AI system |
| 5.5.8. | Opportunities for swapping copper interconnects to optical connects |
| 5.5.9. | Nvidia's 3D integration of SoC, HBM, EIC and PIC on co-packaged substrates (TSV interposer) |
| 5.5.10. | AMD |
| 5.5.11. | Packaging insights for AMD CPUs |
| 5.5.12. | AMD chip semiconductor packaging roadmap |
| 5.5.13. | AMD EPYC server CPU benchmark |
| 5.5.14. | AMD - 3D V-Cache™ technology |
| 5.5.15. | AMD 3D V-Cache™: Transforming EPYC Processor Performance |
| 5.5.16. | AMD's semiconductor packaging choices for CPU |
| 5.5.17. | Packaging insights for AMD XPUs |
| 5.5.18. | 3D Hybrid bonding for AMD data center XPUs |
| 5.5.19. | AMD Instinct MI300 design concept |
| 5.5.20. | Benchmark: Instinct MI300A vs MI300X |
| 5.5.21. | AMD Instinct MI300: connectivity |
| 5.5.22. | Packaging structure for MI300 family |
| 5.5.23. | AMD patents GPU chiplet design for future graphics cards |
| 5.5.24. | AMD GPU memory choice for different applications |
| 5.5.25. | Addressing Power Consumption Challenges in Expanding Computing System |
| 5.5.26. | Xilinx FPGA packaging |
| 5.5.27. | Future system-in-package architecture |
| 5.5.28. | Intel |
| 5.5.29. | Intel products for HPC |
| 5.5.30. | Intel Xeon server processor Roadmap |
| 5.5.31. | Advanced semiconductor packaging for Intel Xeon processors - 1: Sapphire Rapids |
| 5.5.32. | Advanced semiconductor packaging for Intel Xeon processors - 2: Sierra Forest |
| 5.5.33. | Advanced semiconductor packaging for Intel Xeon processors - 3: Clearwater Forest |
| 5.5.34. | Advanced semiconductor packaging for Intel data center GPU: Ponte Vecchio (1) |
| 5.5.35. | Advanced semiconductor packaging for Intel data center GPU: Ponte Vecchio (2) |
| 5.5.36. | Advanced semiconductor packaging for Intel data center GPU: Ponte Vecchio (3) |
| 5.5.37. | Advanced semiconductor packaging for Intel data center GPU: Ponte Vecchio (4) |
| 5.5.38. | Intel FPGA packaging |
| 5.5.39. | Intel Lakefield packaging insights |
| 5.5.40. | Intel Lakefield packaging teardown |
| 5.5.41. | HPC: Summary |
| 5.5.42. | How future HPC platform would look like? |
| 5.5.43. | High-end commercial chips based on advanced semiconductor packaging technology (1) |
| 5.5.44. | High-end commercial chips based on advanced semiconductor packaging technology (2) |
| 5.6. | Automotive |
| 5.6.1. | Future ADAS/Autonomous driving systems: requirements, actions, and current challenges |
| 5.6.2. | Three transformational pillars in automotive electronics |
| 5.6.3. | Autonomous vehicles (AVs) - an overview |
| 5.6.4. | The Automation Levels in Detail |
| 5.6.5. | Typical Sensor Suite for Autonomous Cars |
| 5.6.6. | The Coming Flood of Data in Autonomous Vehicles |
| 5.6.7. | High demand for computing power in autonomous vehicles |
| 5.6.8. | Semiconductor content increase in AVs |
| 5.6.9. | Autonomous driving platform - processors and chip packaging |
| 5.6.10. | The primary differentiators for AVs will be chip design and software |
| 5.6.11. | Autonomous driving platform - processors and packaging roadmap (1) |
| 5.6.12. | Autonomous driving platform - processors and packaging roadmap (2) |
| 5.6.13. | Chip design and packaging choice for AV computing processers from different suppliers |
| 5.6.14. | NVIDIA's AV computing modules for L5 automotive |
| 5.6.15. | Self-driving computing module packaging challenges |
| 5.6.16. | Autonomous vertical integration |
| 5.6.17. | Automotive advance packaging - TSMC roadmap |
| 5.6.18. | Autonomous - packaging for sensors |
| 5.6.19. | Packaging for sensors in ADAS (1) |
| 5.6.20. | Packaging for sensors in ADAS (2) |
| 5.6.21. | Future radar packaging choices |
| 5.6.22. | Radar IC packages |
| 5.7. | Antenna in Package (AiP) for 5G and 6G |
| 5.7.1. | 5G&6G development and standardization roadmap |
| 5.7.2. | Mobile Telecommunication Spectrum and Network Deployment Strategy |
| 5.7.3. | 5G Commercial/Pre-commercial Services by Frequency |
| 5.7.4. | mmWave now and future |
| 5.7.5. | Global trends and new opportunities in 5G/6G |
| 5.7.6. | Overview of challenges, trends and innovations for high frequency communication (mmWave & THz) devices |
| 5.7.7. | Navigating Challenges and Solutions in mmWave phased array system |
| 5.7.8. | Integration requirement for phased array |
| 5.7.9. | Antenna packaging requirement |
| 5.7.10. | Benchmarking three antenna packaging technologies |
| 5.7.11. | The goal of next generation phased array |
| 5.7.12. | Overview of antenna packaging technologies vs operational frequency |
| 5.7.13. | Antenna-in-Package (AiP) vs Conventional Discrete Antenna Techniques in Wireless Systems |
| 5.7.14. | Key Design Considerations for AiP |
| 5.7.15. | Overview of low-loss materials for phased array substrate |
| 5.7.16. | Dk and Df comparison of material for phased array substrate |
| 5.7.17. | Other Material Requirement for Phased Array Substrate |
| 5.7.18. | Benchmark of substrate material properties for AiP |
| 5.7.19. | Benchmark of substrate technology for AiP |
| 5.7.20. | Trend: Choices of low-loss materials for AiP |
| 5.7.21. | Summary of substrate technology for AiP |
| 5.7.22. | Flip-chip vs Fan-out AiP: Benchmark |
| 5.7.23. | Choices of antenna packaging technologies for 6G |
| 5.7.24. | Antenna on chip (AoC) for 6G |
| 5.7.25. | Methods to improve antenna performance in AoC |
| 5.7.26. | Roadmap for antenna packaging development for 6G |
| 5.7.27. | Key trends for EMI shielding implementation |
| 5.7.28. | Choices of packaging technology for AiP |
| 5.7.29. | AiP for 5G mmWave infrastructure shipment forecast 2023-2034 |
| 5.7.30. | mmWave AiP ecosystem |
| 5.8. | 5G infrastructure |
| 5.8.1. | Different RAN architectures |
| 5.8.2. | Samsung's VRAN solution |
| 5.8.3. | Ericsson's cloud RAN solution |
| 5.8.4. | Open RAN deployment based on commercial off-the-shelf (COTS) hardware |
| 5.8.5. | Ultra-low latency networks require accelerator card |
| 5.8.6. | Open RAN infrastructure arrangement |
| 5.8.7. | Software defined radio (SDR) |
| 5.8.8. | Massive MIMO (mMIMO) |
| 5.8.9. | Block diagram of MIMO antenna array system |
| 5.8.10. | Integration of digital frontend with transceivers |
| 5.8.11. | Si design for Open RAN radio (Analog Devices case) |
| 5.8.12. | Marvell baseband Si for 5G Open RAN radio |
| 5.8.13. | Marvell SoC for 5G networks (2) |
| 5.8.14. | Xilinx's Si solution for 5G radio unit (1) |
| 5.8.15. | Xilinx's Si solution for 5G radio unit (2) |
| 5.8.16. | End-to-end 5G silicon solutions from intel |
| 5.8.17. | Intel's FPGA for 5G radio (1) |
| 5.8.18. | Intel's FPGA for 5G radio (2) |
| 5.8.19. | The intentions of 5G system vendors enter Si battleground |
| 5.8.20. | 5G base station types: macro cells and small cells |
| 5.9. | Consumer electronics |
| 5.9.1. | Advanced semiconductor packaging technologies for consumer electronics |
| 5.9.2. | Commercialized high density fan-out packaging solutions |
| 5.9.3. | Samsung's new galaxy smartwatch |
| 5.9.4. | Packaging choices for packaging application processor environments (APEs) in consumer electronics (1) |
| 5.9.5. | Packaging choices for packaging application processor environments (APEs) in consumer electronics (2) |
| 5.9.6. | 3D packaging for APE in consumer electronics |
| 5.9.7. | Future packaging trend for APE in consumer electronics |
| 5.9.8. | Apple's M1 ultra for workstations uses TSMC's fan-out technologies |
| 5.9.9. | AMD Stacked 3D V-Cache technology for consumer desktop CPU |
| 5.9.10. | Intel mobile SoC for laptops (Lakefield) advanced semiconductor packaging |
| 5.9.11. | Advanced semiconductor packaging in Intel's next generation CPU Meteor Lake |
| 6. | MONOLITHIC 3D IC |
| 6.1. | From 2D system to Monolithic 3D IC (M3D) |
| 6.2. | The driving force for Monolithic 3D IC |
| 6.3. | 3D Integration technology landscape |
| 6.4. | Significantly improved interconnect density with M3D (1) |
| 6.5. | Significantly improved interconnect density with M3D (2) |
| 6.6. | Heterogenous 3D vs Monolithic 3D |
| 6.7. | What are the challenges in making monolithic 3D IC |
| 6.8. | 2D Materials for upper layer transistor in Monolithic 3D IC |
| 6.9. | CNTs for transistors |
| 6.10. | CNFET research breakthrough (1) |
| 6.11. | CNFET research breakthrough (2) |
| 6.12. | CNFET case study |
| 6.13. | Solutions? |
| 6.14. | Future applications of M3D |
| 6.15. | Future outlook and key takeaway |
| 7. | MARKET FORECAST SUMMARY |
| 7.1. | Data center server unit forecast 2023-2035 (shipment) |
| 7.2. | Intel vs AMD for Server CPUs |
| 7.3. | Future packaging trend for chiplet server CPU |
| 7.4. | Total addressable data center CPU market forecast 2023-2035 (Shipment) |
| 7.5. | Data center CPU: advanced semiconductor packaging unit forecast 2025-2035 (shipment) |
| 7.6. | Accelerators in servers -1 |
| 7.7. | Accelerators in servers -2 |
| 7.8. | Server board layout - with accelerators (1) |
| 7.9. | Server board layout - with accelerators (2) |
| 7.10. | Total addressable data center accelerator market forecast 2023-2035 (Shipment) |
| 7.11. | Data center accelerator: advanced semiconductor packaging unit forecast 2023-2035 (shipment) |
| 7.12. | L4+ Autonomous vehicles sales forecast 2022-2045 |
| 7.13. | Total addressable ADAS processor & accelerator sales market for L4+ autonomous vehicles forecast 2022-2045 |
| 7.14. | 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045 |
| 7.15. | 3D advanced semiconductor packaging unit sales for L4+ autonomous vehicles forecast 2022-2045 |
| 7.16. | Advanced semiconductor packaging unit forecast for APE in consumer electronics remarks |
| 7.17. | Unit sales forecast for smartphones/tablets/smartwatches/AR/VR/MR 2023-2035 |
| 7.18. | Advanced semiconductor packaging unit forecast for APE (application processor environment) in consumer electronics 2023-2035 (1) |
| 7.19. | Advanced semiconductor packaging unit forecast for APE (application processor environment) in consumer electronics 2023-2035 (2) |
| 7.20. | Global PC shipment forecast 2023-2035 |
| 7.21. | Advanced semiconductor packaging units in PC forecast 2023-2035 (1) |
| 7.22. | Advanced semiconductor packaging units in PC forecast 2023-2035 (2) |
| 7.23. | 5G radios by MIMO size unit forecast 2023-2035 (cumulative) |
| 7.23.1. | Estimating the total addressable market for advanced semiconductor packaging in 5G RAN infrastructure 2023-2035 (cumulative) |
| 7.23.2. | Advanced semiconductor packaging unit for 5G RAN networks 2023-2035 (cumulative) |
| 8. | COMPANY PROFILES |
| 8.1. | List of company profiles |
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คาดการณ์ว่า CAGR 25% สำหรับการเติบโตของบรรจุภัณฑ์เซมิคอนดักเตอร์ขั้นสูงในภาคส่วน HPC
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