先端半導体パッケージング 2025-2035年：予測、技術、用途

● 全体概要

● 先端半導体パッケージング紹介

□ トランジスタ微細化の課題

□ チップレットの台頭

□ 先端半導体パッケージング技術の台頭

● 2.5Dパッケージングと3Dパッケージングの徹底解説。各業界動向（新旧比較）、技術ベンチマーク（シリコン、有機、ガラス）、各材料の障壁分析掲載。

□ 先端半導体パッケージング技術 - 技術の概要

□ 2.5Dパッケージング

□ 2.5Dシリコン系パッケージング

□ 2.5D有機系パッケージング

□ 2.5Dガラス系パッケージング

□ 技術ベンチマーク： シリコン・有機・ガラス

□ 3Dハイブリッドボンディング

● プレーヤー分析 - 技術、ロードマップ、顧客、今後の見通し

□ TSMCの先端半導体パッケージングソリューション

□ インテルの先端半導体パッケージングソリューション

□ サムスンの先端半導体パッケージングソリューション

□ ASEの先端半導体パッケージングソリューション

□ アムコーの先端半導体パッケージングソリューション

● 市場での用途 - 概要、パッケージングのトレンド新旧比較、事例紹介、市場展望

□ ハイパフォーマンスコンピューティング（HPC）向けチップ

□ CPO（コ・パッケージド・オプティクス）

□ HBM（高帯域幅メモリ）

□ 大手企業によるHPCシステムのパッケージング戦略

□ 自動車

□ 5G/6G向けAiP（アンテナ・イン・パッケージ）

□ 5Gインフラ

□ 家電製品

● モノリシック3D（M3D）

□ はじめに

□ M3Dの課題

□ M3D用材料

□ 用途と今後のロードマップ

● 市場予測の概要

 

 

Semiconductor packaging has evolved from traditional 1D PCB designs to cutting-edge 3D hybrid bonding at the wafer level. This advancement allows for interconnect pitches in the single-digit micrometer range and bandwidths up to 1000 GB/s, all while maintaining high energy efficiency. Central to advanced semiconductor packaging technologies are 2.5D packaging—where components are positioned side by side on an interposer—and 3D packaging, which involves stacking active dies vertically. These technologies are critical for the future of HPC systems.

 

2.5D packaging technologies involve various interposer materials, each offering distinct advantages and drawbacks. Silicon (Si) interposers, which include full passive Si wafers and localized Si bridges, are known for facilitating the finest routing features, making them ideal for high-performance computing. However, they come with high costs in both materials and manufacturing, and face limitations in packaging area. To mitigate these issues, the use of localized Si bridges is increasing, strategically utilizing silicon where fine features are essential and addressing area constraints.

 

Organic interposers, which use a fan-out molding compound, offer a more cost-effective alternative to silicon. They have a lower dielectric constant, which reduces RC delay in the package. Despite these benefits, organic interposers struggle to achieve the same level of interconnect feature reduction as silicon-based packages, limiting their adoption in high-performance computing applications.

 

Glass interposers have gained significant interest, particularly after Intel's recent unveiling of a glass-based test vehicle package. Glass offers advantageous properties such as a tunable Coefficient of Thermal Expansion (CTE), high dimensional stability, a smooth as well as flat surface, and the ability to enable panel manufacturing, making it a promising candidate for interposers with routing features that could rival silicon. However, the main drawback of glass interposers is the immature ecosystem and the current lack of large-scale production capabilities, in addition to its technical challenges. As the ecosystem matures and production capabilities improve, glass-based technologies in semiconductor packaging may see further growth and adoption.

 

Regarding 3D packaging technologies, Cu-Cu bumpless hybrid bonding is emerging as a leading innovation. This advanced technique creates permanent interconnections by combining a dielectric material, such as SiO2, with embedded metal (Cu). Cu-Cu hybrid bonding can achieve pitches below 10 micrometers, typically in the single-digit micrometer range, which is a significant improvement over conventional microbump technology, which has a bump pitch of around 40-50 micrometers. The benefits of hybrid bonding include increased I/O, higher bandwidth, improved 3D vertical stacking, enhanced power efficiency, and reduced parasitics and thermal resistance due to the absence of underfill. However, this technique is complex to manufacture and comes with higher costs.

 

 

The 2.5D and 3D packaging technologies encompass various packaging techniques. In 2.5D packaging, the choice of interposer material categorizes it into Si-based, Organic-based, and glass-based interposers, as illustrated in the figure above. Meanwhile, in 3D packaging, the evolution of microbump technology aims for smaller pitch dimensions. However, achieving single-digit pitch dimensions today is made possible through the adoption of hybrid bonding technology, a method that directly connects Cu-Cu, indicating a significant advancement in the field.

 

 

IDTechEx has previously predicted that 2.5D silicon bridge solutions will soon replace silicon interposers as the primary choice for packaging HPC chips, due to the limitations of silicon interposers, which struggles to exceed 3x reticle sizes. TSMC, a key provider of 2.5D silicon interposers to NVIDIA and other major HPC developers like Google and Amazon, recently announced high-volume production of its first-generation CoWoS_L at 3.5x reticle size. IDTechEx expects this trend to continue, with further advancements explored in their report covering key players.

 

Panel-level packaging has become a significant focus, as highlighted at Semicon Taiwan 2024. This packaging method allows for larger interposers and helps reduce costs by enabling the production of more packages simultaneously. Despite its potential, challenges such as warpage management still need to be addressed. Its growing prominence reflects the increasing demand for larger and more cost-effective interposers.

 

Glass is emerging as a strong candidate for enabling fine routing, comparable to silicon, with added benefits like tunable coefficient of thermal expansion (CTE) and improved reliability. Glass interposers are also compatible with panel-level packaging, offering the potential for high-density routing at a more manageable cost, making them a promising solution for future packaging technologies.

3D copper-copper (Cu-Cu) hybrid bonding is a critical technology for enabling ultra-fine pitch vertical interconnects between chips. This technology has already been used in several high-end server products, including AMD's EPYC for stacking SRAM and CPUs, and the MI300 series for stacking CPU/GPU tiles on I/O tiles. Hybrid bonding is expected to play a pivotal role in future HBM advancements, particularly for DRAM stacks beyond 16-Hi or 20-Hi layers.

 

Optical interconnect technology has gained considerable traction, driven by the growing need for higher data throughput alongside improved power efficiency. Co-packaged optics (CPO) is emerging as a key solution to enhance I/O bandwidth and reduce energy consumption. Optical communication offers multiple advantages over traditional electrical transmission, including lower signal degradation over distance, reduced susceptibility to crosstalk, and significantly higher bandwidth. These benefits make CPO an ideal fit for data-intensive, power-efficient HPC systems.

 

The primary market driving the development of 2.5D and 3D packaging technologies is undoubtedly the high-performance computing (HPC) sector. These advanced packaging methods are crucial in overcoming the limitations of Moore's law, enabling more transistors, memory, and interconnections within a single package. The disaggregation of chips also allows for optimal process node utilization across different functional blocks, such as separating I/O tiles from processing tiles, further enhancing efficiency.

 

Beyond HPC, other markets are poised for growth through the adoption of advanced packaging technologies. In the 5G and 6G sectors, innovations like antenna-in-package and cutting-edge chip solutions will shape the future of radio access network (RAN) architectures. Autonomous vehicles will also benefit, as these technologies support the integration of sensor suites and computing units to process large volumes of data while ensuring safety, reliability, compactness, power and thermal management, and cost-effectiveness.

 

Consumer electronics—including smartphones, smartwatches, AR/VR devices, PCs, and workstations—though more cost-conscious, are increasingly focused on handling more data within smaller spaces. Advanced semiconductor packaging will play a key role in this trend, though the packaging methods will differ from those used in HPC. IDTechEx provides in-depth analysis of these industries, examining how advanced packaging technologies will impact them and offering market forecasts.

 

 

 

The report "Advanced Semiconductor Packaging 2025-2035" thoroughly explores the latest innovations in semiconductor packaging technology, covering key technical trends, analyzing the value chain, evaluating major players, and providing detailed market forecasts.

 

Recognizing the crucial role of advanced semiconductor packaging as the foundation for next-generation ICs, the report focuses on its applications in key markets such as AI and data centers, 5G, autonomous vehicles, and consumer electronics. Leveraging IDTechEx's expertise in these sectors, the report delivers a comprehensive understanding of the impact and future trajectory of advanced semiconductor packaging in these critical fields.

 

Exploring Technology Trends and Manufacturers in Advanced Semiconductor Packaging:

 

10-year Granular Market Forecasts & Analysis:

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担当: 村越美和子 m.murakoshi@idtechex.com