半導体産業を一変させるチップレット市場は2035年までに4110億ドル規模にまで成長

チップレット技術 2025-2035年:技術、機会、用途

モジュール設計、サプライチェーンの回復力、異種材料集積、先端パッケージング、先進インターコネクトと通信、熱管理ソリューション


製品情報 概要 目次 価格 Related Content
本レポートでは、ムーアの法則の鈍化に伴って柔軟性とコスト効率が求められていることを背景に、チップレット技術が半導体設計を一変する影響力について考察します。集積、インターコネクトと通信、熱管理などの課題を取り上げながら、サプライチェーンの関連プレーヤーの発展に焦点を当てています。本レポートでご覧いただける10年間の市場予測では、サーバー、通信、PC、携帯電話機、自動車の各産業におけるアプリケーションにより、2035年までに4110億ドル規模に成長すると見込んでいます。主要技術、市場動向、サプライチェーンの動態に関する洞察を提供するなど、チップレットの動向を理解する上で必須の資料となっています。
「チップレット技術 2025-2035年」が対象とする主なコンテンツ
(詳細は目次のページでご確認ください)
● 全体概要および結論
□ 10年間の市場予測
□ サプライチェーン分析
□ 半導体業界動向への影響
● チップレット技術の紹介
● チップレット設計の推進要因と利点
● 導入と実装における課題
● 技術と製造プロセス
□ 設計手法
□ パッケージング技術
□ チップレット間通信
□ インターコネクトと規格
□ 熱管理戦略
● チップレット技術の用途とユースケース
 
「チップレット技術 2025-2035年」は以下の情報を提供します
チップレットの背景と目的 
  • チップレット技術とそれが半導体設計に変革をもたらす影響力の概要
  • チップレット設計が注目を集める推進要因と利点分析(柔軟性、モジュール性、コスト効率など)
  • チップレットが従来のモノリシック設計が抱える制約をどのように解消し、歩留まり向上とコスト引き下げを実現するかを解説
チップレット技術と課題
  • 技術と製造プロセスに関する洞察(主に設計手法とパッケージング技術)
  • シームレスな集積を実現するインターコネクトと規格の詳細を明らかにし、チップレット間通信を解説
  • 高密度集積化を実現するチップレットシステムに効果的な熱管理戦略
  • チップレット技術を導入時の課題(集積の複雑さや熱管理問題など)
市場予測と現状分析
  • 包括的市場予測(2035年までの成長傾向と未来予測も掲載)
  • 6つの応用分野(サーバー、通信・5G・IoT、PC、携帯電話機、自動車産業、その他)の10年間予測を網羅する詳細分析
  • 有力企業と成長著しいチップレット技術での企業が担う役割と現在の市場状況と動向解説
  • 有力企業と成長著しいチップレット技術での企業が担う役割とサプライチェーンの詳細分析
 
In the rapidly evolving world of semiconductors, chiplet technology is emerging as a groundbreaking approach that addresses many of the challenges faced by traditional monolithic System-on-Chip (SoC) designs. As Moore's Law slows down, the semiconductor industry is seeking innovative solutions to increase performance and functionality without merely increasing transistor density. Chiplets offer a promising path forward, providing flexibility, modularity, customizability, efficiency, and cost-effectiveness in chip design and manufacturing. Companies like AMD and Intel have been at the forefront of this technology, with products like AMD's EPYC processors and Intel's Ponte Vecchio data center GPU showcasing the potential of chiplets in boosting core counts and integrating diverse functionalities.
 
Chiplets are discrete modular semiconductor components that are co-designed and manufactured separately before being integrated into a larger system. This approach resembles a SoC on a module, where each chiplet is designed to function in conjunction with others, necessitating co-optimization in design. The modularity of chiplets aligns with key semiconductor trends such as IP chipletization, integration heterogeneity, and I/O incrementalization. Chiplet is also associated with heterogeneous integration and advanced packaging.
 
SoC vs Chiplet concept
 
Why Chiplets Are Gaining Traction
The slowdown of Moore's Law has made it increasingly difficult to add more transistors within a limited area. Instead, the focus has shifted to enhancing function density—an area where chiplet design excels. In the meantime, development efforts have increasingly focused on system-level integration rather than solely on wafer manufacturing.
 
The adoption of chiplet technology is driven by its ability to address several critical limitations inherent in traditional monolithic chip designs. One advantage is its capacity to overcome constraints such as reticle size and the memory wall, which traditionally hinder the performance and scalability of semiconductor devices. By modularizing chip functions into discrete chiplets, manufacturers can optimize the use of semiconductor materials and processing nodes more effectively. In addition, chiplets can achieve better utilization of wafer corner space and have lower defect rate on chips, which are often underutilized in conventional chip designs, particularly in larger SoCs that demand an increasing number of functions. The discrete components can be tested and validated individually before integration. As a result, the manufacturing yield increases, allowing for higher output quality and reduced costs per unit. Furthermore, chiplets facilitate a more flexible design process, enabling the integration of diverse functionalities tailored to specific applications without the need for entirely new chip designs. This flexibility not only reduces development time and costs but also allows for rapid adaptation to evolving technological demands.
 
The nature of chiplets allows manufacturers to source different parts from multiple suppliers across various regions. This diversification reduces dependency on any single supplier or geographic area, thereby enhancing supply chain resilience. In the context of geopolitical tensions and trade restrictions, chiplet technology provides a strategic advantage by mitigating risks associated with supply disruptions. By adopting chiplet designs, companies can navigate these constraints more effectively, ensuring a steady supply of critical components without relying heavily on regions subject to political instability or trade sanctions.
 
Collectively, these factors make chiplet technology an attractive option for manufacturers seeking to enhance performance while maintaining economic efficiency.
 
New functions/designs enabled by chiplet design
 
Current Market Landscape
The global market for chiplets is experiencing remarkable growth. Being projected to reach US$411 billion by 2035, driven by high-performance computing demands across sectors such as data centers and AI. The modular nature of chiplets allows for rapid innovation and customization, catering to specific market needs while reducing development timelines and costs.
 
While chiplets offer numerous advantages, they also present new challenges. The integration of multiple chiplets requires advanced interconnection technologies and standards to ensure seamless communication between components. Thermal management is another critical area, as increased function density can lead to overheating if not properly managed. These challenges open up opportunities for various players in the supply chain. For instance, different areas of the package in chiplet design require distinct types of underfill materials to address specific needs, e.g. to protect the chips themselves, providing mechanical support and thermal stability, as well as to safeguard the delicate wires and solder balls that connect the chiplets, preventing issues such as delamination or separation. This creates demand for innovative materials that enhance reliability and performance.
 
Report Coverage
The report provides a comprehensive analysis of the chiplet technology landscape, beginning with an executive summary offers an overview of the report's findings and insights, setting the stage for a detailed introduction to the basics of chiplet technology. The report explores the drivers and benefits that make chiplet design attractive, while also identifying the challenges and hurdles in its adoption and implementation. It provides insights into technology and manufacturing processes, including design methodologies and packaging techniques. The discussion extends to inter-chiplet communication, focusing on interconnects and standards necessary for seamless integration. Thermal management strategies are outlined to address heat management in densely packed systems. Finally, the report examines various application areas, showcasing use cases across different sectors that demonstrate the versatility and impact of chiplet technology. A 10-year market forecast segmented by application that examines growth trends and future projections is provided. It also delves into the supply chain, highlighting key players and their roles in advancing chiplet technology.
Key Aspects
 
Chiplet context and motivations
  • Overview of chiplet technology and its transformative impact on semiconductor design.
  • Analysis of drivers and benefits that make chiplet design attractive, such as flexibility, modularity, and cost-effectiveness.
  • Examination of how chiplets address limitations of traditional monolithic designs, improving yields and reducing costs.
 
Chiplet technologies and challenges
  • Insights into technology and manufacturing processes, focusing on design methodologies and packaging techniques.
  • Exploration of inter-chiplet communication, detailing interconnects and standards for seamless integration.
  • Strategies for effective thermal management in densely packed chiplet systems.
  • Identification of challenges in adopting chiplet technology, including integration complexities and thermal management issues.
 
Market forecast and status analysis
  • Comprehensive market forecast with growth trends and future projections up to 2035.
  • Detailed analysis covering a 10-year forecast for six application areas including server, telecommunications & 5G & IoT, PCs, mobile phones, automotive industry and others.
  • Examination of the current market status and trends, highlighting key players and their roles in advancing chiplet technology.
  • Detailed supply chain analysis highlighting key players and their roles in advancing chiplet technology.
Report MetricsDetails
CAGRThe global market for chiplet-form industry will reach US$411 billion by 2035, representing a CAGR of 14.7%
Forecast Period2025 - 2035
Forecast UnitsVolume (unit), value (US$ billion)
Regions CoveredWorldwide
Segments CoveredServer Telecommunications, 5G, IoT PCs Mobile phones Automotive industry Others
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詳細
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アイディーテックエックス株式会社 (IDTechEx日本法人)
担当: 村越美和子 m.murakoshi@idtechex.com
Table of Contents
1.EXECUTIVE SUMMARY
1.1.SoC, SiP vs chiplet
1.2.Current status of chiplet technology
1.3.Future trends in chiplet technology (1/2)
1.4.Future trends in chiplet technology (2/2)
1.5.Possible chiplet supply chain
1.6.Chiplet ecosystem across different periods
1.7.Analysis of possible chiplet supply chain (1/2)
1.8.Analysis of possible chiplet supply chain (2/2)
1.9.Opportunities unlocked by the chiplet platform
1.10.Chiplet impact
1.11.Convergence to chiplet
1.12.Chiplet adoption evolution
1.13.Market forecast coverage and methodologies
1.14.Forecast assumptions
1.15.Chiplet shipment unit forecast 2024-2035
1.16.Chiplet market forecast 2024-2035
1.17.Market share comparison 2024 vs 2030
1.18.Chiplet classifications
1.19.Application markets
1.20.Potential applications of chiplet technology (1/4)
1.21.Potential applications of chiplet technology (2/4)
1.22.Potential applications of chiplet technology (3/4)
1.23.Potential applications of chiplet technology (4/4)
2.INTRODUCTION TO CHIPLETS
2.1.Why now
2.2.From monolithic chips to chiplets
2.3.What is chiplet technology
2.4.Definition of chiplet
2.5.SoC vs Chiplet
2.6.Generic chiplet integration
2.7.SiP vs Chiplet
2.8.Heterogenous integration
2.9.Technology building blocks for heterogeneous integration
2.10.Types of heterogenous integration
2.11.Different types of chiplets for computation
3.DRIVERS AND BENEFITS OF CHIPLET DESIGN
3.1.Limitations of large dies
3.2.Benefits of small chips 1
3.3.Benefits of small chips 2
3.4.Monolithic dies may not provide enough memory
3.5.Increasing cost with advanced processing nodes
3.6.Costs trend with processing nodes
3.7.Costs reduction with processing nodes via Chiplet design
3.8.Improved supply chain security
3.9.IP Chipletization
3.10.Chiplet as a platform
3.11.3D IC design
3.12.Chiplet design for cost consideration
3.13.Other benefits of chiplet design
3.14.The rise of chiplets in semiconductor technology
4.CHALLENGES OF CHIPLET
4.1.Challenges with chiplets
4.2.Challenges from demand and supply angles
5.CHIPLET TECHNOLOGY AND MANUFACTURING
5.1.1.Technical structure of chiplets
5.2.Design
5.2.1.Co-design of high-performance chip-package-system
5.2.2.Chiplet design and integration
5.2.3.Challenges and solutions in EDA for chiplets (1/2)
5.2.4.Challenges and solutions in EDA for chiplets (2/2)
5.2.5.The three giants of EDA are shifting to a new battlefield
5.2.6.AI in EDA
5.3.Packaging and Assembly Technologies
5.3.1.Levels of integration
5.3.2.Traditional packaging
5.3.3.TSV enables integration beyond 2D dimension
5.3.4.From chip, package to system
5.3.5.Dimensionality of advanced packaging
5.3.6.From 1D semiconductor packaging
5.3.7.Advanced packaging 2D & 2D+
5.3.8.Advanced packaging 2.5D & 3D
5.3.9.Advanced packaging 3.5D & 4D
5.3.10.Advanced packaging trend
5.3.11.Key elements of advanced packaging
5.3.12.Silicon stacking: A key enabler of advanced packaging
5.3.13.Trends of advanced packaging
5.3.14.Representative Examples of Advanced Packaging
5.3.15.TSMC's advanced semiconductor packaging technology portfolio
5.3.16.TSMC 2.5D packaging technology - CoWoS
5.3.17.3D chiplet
5.3.18.Combine 3D SoIC and 2.5D backend packaging technologies
5.3.19.Intel's advanced semiconductor packaging technology portfolio
5.3.20.Intel's EMIB
5.3.21.Intel's Co-EMIB (EMIB + Foveros)
5.3.22.Samsung's advanced semiconductor packaging technology portfolio
5.3.23.Samsung's advanced packaging technologies
5.3.24.Amkor advanced semiconductor packaging solutions
5.3.25.Amkor's S-Connect
5.4.Inter-Chiplet Communication and Interconnects
5.4.1.Electrical interconnects
5.4.2.From aluminum to copper
5.4.3.Material considerations
5.4.4.Interconnect technologies for semiconductor packaging
5.4.5.Interface stack for chiplets
5.4.6.Interface for chiplet
5.4.7.D2D interface types
5.4.8.Serial vs parallel interface
5.4.9.112G USR/XSR vs HBI
5.4.10.Proprietary D2D interface standards
5.4.11.Proprietary D2D interface standard comparison
5.4.12.Open D2D interface standards
5.4.13.Open D2D interface standards comparison
5.4.14.Universal Chiplet Interconnect Express (UCIe)
5.4.15.NVIDIA NVLink-C2C
5.4.16.Standard protocols of heterogeneous computing
5.4.17.Relationship of chiplet interfaces, bandwidth and typical packages
5.4.18.Chiplet D2D I/O matrix
5.4.19.Recommended interconnect for applications
5.4.20.Interconnect classification
5.4.21.Interconnection technology I/O pitch & density
5.4.22.Bump technologies
5.4.23.Typical bump sizes and pitches
5.4.24.Hybrid bonding
5.4.25.SoIC compared to 2.5D and 3D IC
5.4.26.Alternative technologies to electric SerDes
5.4.27.Photonics technology for chiplet
5.4.28.Limitation of electrical copper I/O
5.4.29.From discrete III-V to CPO
5.4.30.Optical integration development trends
5.5.Power Delivery and Thermal Management
5.5.1.Power delivery
5.5.2.Power delivery attributes for chiplets
5.5.3.Heat dissipation of a chip
5.5.4.Basics about thermal management
5.5.5.Thermal challenges with chiplet design
5.5.6.Chiplet thermal management strategy
5.5.7.Key materials for packaging chiplet
5.5.8.Thermal interface materials
5.5.9.Strategies for semiconductor TIMs
5.5.10.TIM advancements
5.5.11.Heat sink material solutions
5.5.12.Optimizing heat sink design for advanced architectures
5.5.13.Other materials design consideration for thermal management
5.5.14.Material and process challenges in console failures
5.5.15.Warpage and solder joint issues
5.5.16.Cooling system for chips
5.5.17.Liquid cooling options
5.5.18.Design considerations for in-chip Cooling in 3D Chip stacks
5.5.19.Impingement cooling
5.5.20.Micro-heat pipes
5.5.21.TIM and cooling technologies limits
5.6.Others
5.6.1.Test access architecture
5.6.2.Testing for chiplets:
5.6.3.Chiplet testing
5.6.4.Different test techniques
5.6.5.Repair and redundancy
5.6.6.Antenna effect
5.6.7.Electromagnetic interference in chiplets
6.APPLICATION AREAS AND USE CASES
6.1.Chiplet for high performance computing chips
6.2.Chiplet use cases 1
6.3.Chiplet use cases 2
6.4.Marvell's Mochi
6.5.DARPA's work 1
6.6.DARPA's work 2
6.7.Chiplet architecture used in Apple chips
6.8.Apple's UltraFusion technology
6.9.Intel's contributions to chiplet
6.10.Intel's Ponte Vecchio
6.11.Intel's Agilex FPGAs
6.12.Intel Gaudi 3
6.13.AMD's chiplet history
6.14.AMD's 1st generation EPYC
6.15.AMD's 2nd generation EPYC
6.16.AMD Chiplet cost
6.17.Genoa and MI300
6.18.AMD's GPU based on chiplet design
6.19.Nvidia B200
6.20.AWS Graviton 4
6.21.Alphawave Semi's efforts
6.22.Ayar Labs' TeraPHY optical I/O chiplet
6.23.The first Chiplet Factory
6.24.Tenstorrent's chiplet technology
6.25.Eliyan's interconnects
6.26.Kiwi Moore's Kiwi SoChiplet Platform
6.27.Japanese automotive chiplet research group
6.28.European chiplet supply chain project
6.29.Imec's automotive chiplet initiative
 

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チップレット技術 2025-2035年:技術、機会、用途

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レポート概要

スライド 192
フォーキャスト 2035
発行日 Oct 2024
ISBN 9781835700693
 

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