Ultra Low-Power Chip Design of a UHF RFID Tag (RFID Europe 2009)

Ramses Valvekens,
Easics
Belgium
 
Sep 30, 2009.

Downloads

Easics Presentation*

If you already have access, please [Login]

Presentation Summary

  • Challenges and building blocks in semiconductor chip design of EPCglobal Gen-2 passive UHF RFID tags
  • Design techniques including C++ modelling and FPGA prototyping, mixed-signal ASIC design, ultra low-power chip design
  • Unique features of the TegoTag(TM) : large integrated non-volatile memory (32+ Kilobytes), high-reliability and interfacing with sensors, control, displays. In short: "Active functionality in a passive tag."

Speaker Biography (Ramses Valvekens)

Ramses Valvekens is the CEO of Easics. He holds Master degrees in Electronics Engineering and Industrial Engineering from the Katholieke Universiteit Leuven and Groep T (Leuven, Belgium). He performed research at the Lawrence Livermore National Laboratories (California,
USA) and at the Institut National Polytechnique de Grenoble (France).
He won the Barco/VIK prize in 1994 for the design of a reconfigurable processor for industrial image processing in cooperation with IMEC.
He received the TranSwitch Employee Recognition Award in 2003, and holds two telecommunication patents. Previously, he was a technical manager responsible for a product family of mixed-signal telecom chips.

Company Profile (Easics)

Easics logo
Easics is an independent System-on-Chip design company, founded in 1991. Easics designs future-proof and robust high-performance embedded systems for leading OEMs and semiconductor companies. Easics' Systems-on-Chip are realized in both digital & mixed-signal ASIC- and FPGA-technology. Easics' expertise and IP includes connectivity, hardware/software co-design, digital signal processing and low-power design. Easics' customer base consists of leading companies, active in industrial, measurement, consumer, wired & wireless telecom, RFID, and medical markets.
View Easics Timeline